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iif.htm
Enumerations
IifList
Instruction handlers
F2XM1 F4X4 FABS FADD FADDP FBLD FBSTP FCLEX FCMOVB FCMOVBE FCMOVE FCMOVNB FCMOVNBE FCMOVNE FCMOVNU FCMOVU FCOM FCOM2 FCOMI FCOMIP FCOMP FCOMP3 FCOMP5 FCOMPP FCOS FDECSTP FDISI FDIV FDIVP FDIVR FDIVRP FENI FFREE FFREEP FCHS FIADD FICOM FICOMP FIDIV FIDIVR FILD FIMUL FINCSTP FINIT FIST FISTP FISTTP FISUB FISUBR FLD FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ FMUL FMUL4X4 FMULP FNCLEX FNDISI FNENI FNINIT FNOP FNSAVE FNSETPM FNSTCW FNSTENV FNSTSW FPATAN FPREM FPREM1 FPTAN FRICHOP FRINEAR FRINT2 FRNDINT FRSTOR FRSTPM FSAVE FSBP0 FSBP1 FSBP2 FSBP3 FSCALE FSETPM FSIN FSINCOS FSQRT FST FSTCW FSTDW FSTENV FSTP FSTP1 FSTP8 FSTP9 FSTSG FSTSW FSUB FSUBP FSUBR FSUBRP FTST FUCOM FUCOMI FUCOMIP FUCOMP FUCOMPP FWAIT FXAM FXCH FXCH4 FXCH7 FXRSTOR FXRSTOR64 FXSAVE FXSAVE64 FXTRACT FYL2X FYL2XP1 WAIT

↑ IifHandlers

assemble floating-point machine instructions.

See also

IiHandlers, [IntelVol2].

iif PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
 INCLUDEHEAD "euroasm.htm" ; Interface (structures, symbols and macros) of other modules.

iif HEAD ; Start of module interface.

↑ %IifList

enumerates machine instructions of this family which €ASM can assemble.
Each instruction declared in %IifList requires the corresponding handler in this file.

See also

DictLookupIi

%IifList %SET \
FWAIT, \
WAIT, \
FILD, \
FINIT, \
FLD, \
FST, \
FIST, \
FISTP, \
FISTTP, \
F2XM1, \
FABS, \
FADD, \
FADDP, \
FBLD, \
FBSTP, \
FCHS, \
FCLEX, \
FCMOVB, \
FCMOVBE, \
FCMOVE, \
FCMOVNB, \
FCMOVNBE, \
FCMOVNE, \
FCMOVNU, \
FCMOVU, \
FCOM, \
FCOMI, \
FCOMIP, \
FCOMP, \
FCOMPP, \
FCOS, \
FDECSTP, \
FDISI, \
FDIV, \
FDIVP, \
FDIVR, \
FDIVRP, \
FENI, \
FFREE, \
FFREEP, \
FIADD, \
FICOM, \
FICOMP, \
FIDIV, \
FIDIVR, \
FIMUL, \
FINCSTP, \
FISUB, \
FISUBR, \
FLD1, \
FLDCW, \
FLDENV, \
FLDL2E, \
FLDL2T, \
FLDLG2, \
FLDLN2, \
FLDPI, \
FLDZ, \
FMUL, \
FMULP, \
FNCLEX, \
FNDISI, \
FNENI, \
FNINIT, \
FNOP, \
FNSAVE, \
FNSTCW, \
FNSTENV, \
FNSTSW, \
FPATAN, \
FPREM, \
FPREM1, \
FPTAN, \
FRNDINT, \
FRSTOR, \
FSAVE, \
FSCALE, \
FSETPM, \
FSIN, \
FSINCOS, \
FSQRT, \
FSTCW, \
FSTENV, \
FSTP, \
FSTSW, \
FSUB, \
FSUBP, \
FSUBR, \
FSUBRP, \
FTST, \
FUCOM, \
FUCOMI, \
FUCOMIP, \
FUCOMP, \
FUCOMPP, \
FXAM, \
FXCH, \
FXRSTOR, \
FXRSTOR64, \
FXSAVE, \
FXSAVE64, \
FXTRACT, \
FYL2X, \
FYL2XP1, \
FTSTP, \
FRICHOP, \
FRINT2, \
FRINEAR, \
FCOM2, \
FCOMP3, \
FCOMP5, \
FSTP1, \
FSTP8, \
FSTP9, \
FXCH7, \
FSTSG, \
FSTDW, \
FXCH4, \
FRSTPM, \
FNSETPM, \
F4X4, \
FMUL4X4, \
FSBP0, \
FSBP1, \
FSBP2, \
FSBP3, \

;

  ENDHEAD iif ; End of module interface.

↑ FCMOVB

FP Conditional Move - below (CF=1)

Comment

IifFCMOVB is a common handler for FP instructions which calculate the result of mathematic operation with numbers in two FP registers. Both the first operand and destination is always ST0. The second operand is ST0..ST7.

Reference

Finstr ST0, STi	destination=ST0, source=STi
Finstr STi	destination=ST0, source=STi
Finstr	destination=ST0, source=ST1

See also

FCMOVB, FCMOVE, FCMOVBE, FCMOVU, FCMOVNB, FCMOVNE, FCMOVNBE, FCMOVNU, FUCOMI, FCOMI, FUCOMIP, FCOMIP.

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDA /0

Flags

tested:.......C, modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3525

IifFCMOVB:: PROC
      IiEmitOpcode 0xDA
      IiModRM /0
.om:  IiRequire 686,FPU
      IiOpEn M
      IiDispatchFormat none, STi:, STi.STi
.STi.STi:
      IiAbortIfNot Operand1, ST0
.none:IiAssumeEmpty Operand2, ST1
      IiSwap Operand1,Operand2
.STi: RET
 ENDP IifFCMOVB::

↑ FCMOVE

FP Conditional Move - equal (ZF=1)

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDA /1

Flags

tested:....Z..., modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3525

IifFCMOVE:: PROC
    IiEmitOpcode 0xDA
    IiModRM /1
    JMP IifFCMOVB.om:
 ENDP IifFCMOVE::

↑ FCMOVBE

FP Conditional Move - below or equal (CF=1 or ZF=1)

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDA /2

Flags

tested:....Z..., modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3525

IifFCMOVBE:: PROC
    IiEmitOpcode 0xDA
    IiModRM /2
    JMP IifFCMOVB.om:
 ENDP IifFCMOVBE::

↑ FCMOVU

FP Conditional Move - unordered (PF=1)

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDA /3

Flags

tested:......P., modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3525

IifFCMOVU:: PROC
    IiEmitOpcode 0xDA
    IiModRM /3
    MOV BL,0xD8
    JMP IifFCMOVB.om:
 ENDP IifFCMOVU::

↑ FCMOVNB

FP Conditional Move - not below (CF=0)

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDB /0

Flags

tested:.......C, modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3530

IifFCMOVNB:: PROC
    IiEmitOpcode 0xDB
    IiModRM /0
    JMP IifFCMOVB.om:
 ENDP IifFCMOVNB::

↑ FCMOVNE

FP Conditional Move - not equal (ZF=0)

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDB /1

Flags

tested:....Z..., modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3530

IifFCMOVNE:: PROC
    IiEmitOpcode 0xDB
    IiModRM /1
    JMP IifFCMOVB.om:
 ENDP IifFCMOVNE::

↑ FCMOVNBE

FP Conditional Move - below or equal (CF=0 and ZF=0)

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDB /2

Flags

tested:....Z..., modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3530

IifFCMOVNBE:: PROC
    IiEmitOpcode 0xDB
    IiModRM /2
    JMP IifFCMOVB.om:
 ENDP IifFCMOVNBE::

↑ FCMOVNU

FP Conditional Move - not unordered (PF=0)

Category

x87fpu,datamov

Operands

ST,EST

Opcode

0xDB /3

Flags

tested:......P., modified:0123, defined:.1.., undefined:0.23

CPU

PP+

Tested by

t3530

IifFCMOVNU:: PROC
    IiEmitOpcode 0xDB
    IiModRM /3
    JMP IifFCMOVB.om:
 ENDP IifFCMOVNU::

↑ FUCOMI

Unordered Compare Floating Point Values and Set EFLAGS

Description

FUCOMI

Category

x87fpu,compar

Operands

ST,EST

Opcode

0xDB /5

Flags

modified:O...Z.PC .1.., defined:O...Z.PC .1.., values:O.......

CPU

PP+

Tested by

t3530

IifFUCOMI:: PROC
    IiEmitOpcode 0xDB
    IiModRM /5
    JMP IifFCMOVB.om:
 ENDP IifFUCOMI::

↑ FCOMI

Compare Floating Point Values and Set EFLAGS

Description

FCOMI

Category

x87fpu,compar

Operands

ST,EST

Opcode

0xDB /6

Flags

modified:O...Z.PC .1.., defined:O...Z.PC .1.., values:O.......

CPU

PP+

Tested by

t3530

IifFCOMI:: PROC
    IiEmitOpcode 0xDB
    IiModRM /6
    JMP IifFCMOVB.om:
 ENDP IifFCOMI::

↑ FUCOMIP

Unordered Compare Floating Point Values and Set EFLAGS and Pop

Description

FUCOMIP

Category

x87fpu,compar

Operands

ST,EST

Opcode

0xDF /5

Flags

modified:O...Z.PC .1.., defined:O...Z.PC .1.., values:O.......

CPU

PP+

Tested by

t3530

IifFUCOMIP:: PROC
    IiEmitOpcode 0xDF
    IiModRM /5
    JMP IifFCMOVB.om:
 ENDP IifFUCOMIP::

↑ FCOMIP

Compare Floating Point Values and Set EFLAGS and Pop

Description

FCOMIP

Category

x87fpu,compar

Operands

ST,EST

Opcode

0xDF /6

Flags

modified:O...Z.PC .1.., defined:O...Z.PC .1.., values:O.......

CPU

PP+

Tested by

t3530

IifFCOMIP:: PROC
    IiEmitOpcode 0xDF
    IiModRM /6
    JMP IifFCMOVB.om:
 ENDP IifFCOMIP::

↑ FADD

FP Add

Description

FADD

Comment

FADD and similar are instructions with opcode 0xD8 or 0xDC, which calculate the result of mathematic operation with two FP numbers. One source is always ST0, the second source is either ST0..ST7 or memory operand with single or double precision FP value.
Result of the operation is stored back to ST0 or to ST0..ST7.

Reference

FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR,

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | ST,Mdr | EST,ST

Opcode

0xD8 ^mf /0 | 0xD8 ^mf /0 | 0xDC ^Mf /0 | 0xDC /0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3550

IifFADD:: PROC
     IiModRM /0
.rm: IiRequire 086,FPU
     IiAllowModifier CODE
     IiOpEn M
     IiDataSize FloatingPoint=ON
     IiDispatchFormat STi.STi, STi:, STi.m64, STi.m32, m64, m32, none
.STi.m32:
     IiEmitOpcode 0xD8
     IiEncoding CODE=SHORT
 .op:IiAbortIfNot Operand1, ST0
     IiSwap Operand1,Operand2
     RET
.STi.m64:
     IiEmitOpcode 0xDC
     IiEncoding CODE=LONG
     JMP .op:
.STi:IiAssumeEmpty Operand2,ST0
.STi.STi:
     IiAbortIfNotST0
     JC  .SR:  ; If F* STi,ST0
     JNZ .SW:  ; If F* ST0,STi
     IiDispatchCode LONG=.SR: ; If both operands are ST0,ST0, let user choose opcode D8 or DC.
 .SW:IiSwap Operand1,Operand2
.m32:IiEmitOpcode 0xD8
     IiEncoding CODE=SHORT
     RET
.none:IiAssumeEmpty Operand1,ST0
     IiAssumeEmpty Operand2,ST1
     JMP .STi.STi:
 .SR:TESTD [EDI+II.Ppg],0x4000_0000
     JZ .m64: ; If /0, /1, /2, /3.
     XORD [EDI+II.Ppg],0x1000_0000 ; Exchange /4 <-> /5, /6 <-> /7.
.m64:IiEmitOpcode 0xDC
     IiEncoding CODE=LONG
     RET
 ENDP IifFADD::

↑ FMUL

FP Multiply

Description

FMUL

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | ST,Mdr | EST,ST

Opcode

0xD8 ^mf /1 | 0xD8 ^mf /1 | 0xDC ^Mf /1 | 0xDC /1

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3550

IifFMUL:: PROC
     IiModRM /1
     JMP IifFADD.rm:
 ENDP IifFMUL::

↑ FSUB

FP Subtract

Description

FSUB

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | ST,Mdr | EST,ST

Opcode

0xD8 ^mf /4 | 0xD8 ^mf /4 | 0xDC ^Mf /4 | 0xDC /5

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3550

IifFSUB:: PROC
    IiModRM /4
    JMP IifFADD.rm:
 ENDP IifFSUB::

↑ FSUBR

FP Reverse Subtract

Description

FSUBR

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | EST,ST | ST,Mdr

Opcode

0xD8 ^mf /5 | 0xD8 ^mf /5 | 0xDC /4 | 0xDC ^Mf /5

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3550

IifFSUBR:: PROC
    IiModRM /5
    JMP IifFADD.rm:
 ENDP IifFSUBR::

↑ FDIV

FP Divide

Description

FDIV

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | ST,Mdr | EST,ST

Opcode

0xD8 ^mf /6 | 0xD8 ^mf /6 | 0xDC ^Mf /6 | 0xDC /7

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3550

IifFDIV:: PROC
     IiModRM /6
     JMP IifFADD.rm:
 ENDP IifFDIV::

↑ FDIVR

FP Reverse Divide

Description

FDIVR

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | EST,ST | ST,Mdr

Opcode

0xD8 ^mf /7 | 0xD8 ^mf /7 | 0xDC /6 | 0xDC ^Mf /7

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3550

IifFDIVR:: PROC
     IiModRM /7
     JMP IifFADD.rm:
 ENDP IifFDIVR::

↑ FCOM

FP Compare

Comment

IifFCOM is handler for instructions FCOM and FCOMP with opcode 0xD8 or 0xDC, which compare two FP numbers and set condition codes C0,C2,C3 in FPU status word.
One source is always ST0, the other source is either ST0..ST7 or memory operand with single or double precision FP value. Undocumented reversed instructions FCOM2, FCOMP2 behave similar as FCOM, FCOMP with swapped operands.
Operand combinations marked ^€ are €ASM enhancements not documented in vendors specifications.

Reference

FCOM m32	compare ST0 with m32	D8 /2
FCOM€ ST0, m32	compare ST0 with m32	D8 /2
FCOM m64	compare ST0 with m64	DC /2
FCOM€ ST0, m64	compare ST0 with m64	DC /2
FCOM€ ST0, STi	compare ST0 with STi	D8 /2
FCOM STi	compare ST0 with STi	D8 /2
FCOM	compare ST0 with ST1	D8 /2
FCOM€ STi, ST0	compare STi with ST0	DC /2
FCOM2€ STi, ST0	compare STi with ST0	DC /2
FCOM2€ STi	compare STi with ST0	DC /2
FCOM2€	compare ST1 with ST0	DC /2

See also

FCOM, FCOM2, FCOMP, FCOMP3,

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | ST,Mdr | EST,ST

Opcode

0xD8 ^mf /0 | 0xD8 ^mf /0 | 0xDC ^Mf /0 | 0xDC /0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3545

IifFCOM:: PROC
     IiModRM /2
.rm: IiRequire 086,FPU
     IiAllowModifier CODE
     IiOpEn M
     IiDataSize FloatingPoint=ON
     IiDispatchFormat STi.STi, STi:, STi.m64, STi.m32, m64, m32, none
.STi.m32:
     IiAbortIfNot Operand1, ST0
     IiSwap Operand1,Operand2
.m32:IiEmitOpcode 0xD8
     IiEncoding CODE=SHORT
     RET
.STi.m64:
     IiAbortIfNot Operand1, ST0
     IiSwap Operand1,Operand2
.m64:IiEmitOpcode 0xDC
     IiEncoding CODE=LONG
     RET
.none:IiAssumeEmpty Operand1,ST1
.STi:JMP .m32:
.STi.STi:
     IiAbortIfNotST0
     JC .m64:      ; If FCOM  STi,ST0
     JNZ .STi.m32: ; If FCOM  ST0,STi
     IiDispatchCode LONG=.m64: ; If both operands are ST0,ST0, let user choose opcode D8 or DC.
     JMP .m32:
 ENDP IifFCOM::

↑ FCOMP

FP Compare and Pop

Description

FCOMP

Category

x87fpu,compar

Operands

ST,ESsr | ST,ST1 | ST,Mdr

Opcode

0xD8 ^mf /3 | 0xD8D9 /3 | 0xDC ^Mf /3

Flags

modified:0123, defined:0123

Tested by

t3545

IifFCOMP:: PROC
     IiModRM /3
     JMP IifFCOM.rm:
 ENDP IifFCOMP::

↑ FCOM2

FP Compare, alternative

Comment

IifFCOM2 is handler for instructions FCOM2 and FCOMP3 with opcode 0xD8 or 0xDC, which compare two FP numbers and set condition codes C0,C2,C3 in FPU status word.
One source is always ST0, the other source is either ST0..ST7.

Reference

FCOM, FCOM2, FCOMP, FCOMP3,

Category

x87fpu,arith

Operands

ST,Msr | ST,EST | ST,Mdr | EST,ST

Opcode

0xD8 ^mf /0 | 0xD8 ^mf /0 | 0xDC ^Mf /0 | 0xDC /0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3545

IifFCOM2:: PROC
     IiModRM /2
.rm: IiRequire 086,FPU,UNDOC
     IiAllowModifier CODE
     IiOpEn M
     IiDispatchFormat STi.STi, STi:,none
.none:IiAssumeEmpty Operand1,ST1
.STi:IiEmitOpcode 0xDC
     IiEncoding CODE=LONG
     RET
.STi.STi:
     IiAbortIfNotST0
     JC .STi:      ; If FCOM2  STi,ST0
     JNZ .Sw:      ; If FCOM2  ST0,STi
     IiDispatchCode LONG=.STi: ; If both operands are ST0,ST0, let user choose opcode D8 or DC.
 .Sw:IiSwap Operand1,Operand2
     IiEmitOpcode 0xD8
     IiEncoding CODE=SHORT
     RET
 ENDP IifFCOM2::

↑ FCOMP3

FP Reverse Compare and Pop

Category

x87fpu,compar

Operands

ST,ESsr | ST,ST1 | ST,Mdr

Opcode

0xD8 ^mf /3 | 0xD8D9 /3 | 0xDC ^Mf /3

Flags

modified:0123, defined:0123

Tested by

t3545

IifFCOMP3:: PROC
     IiModRM /3
     JMP IifFCOM2.rm:
 ENDP IifFCOMP3::

↑ FIADD

FP Add Integer

Description

FIADD

Comment

FIADD and similar are instructions with opcode 0xDA or 0xDE, which calculate the result of mathematic operation with FP number in ST0 and 16bit or 32bit integer in memory.
Result of the operation is stored to ST0.

Reference

FMUL, FICOM, FICOMP, FISUB, FISUBR, FIDIV, FIDIVR,

Category

x87fpu,arith

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /0 | 0xDE ^MF /0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3580

IifFIADD:: PROC
     IiModRM /0
.rm: IiRequire 086,FPU
     IiOpEn M
     IiDataSize FloatingPoint=ON
     IiDispatchFormat m16,m32,STi.m16,STi.m32
.m32:IiEmitOpcode 0xDA
     RET
.m16:IiEmitOpcode 0xDE
     RET
.STi.m32:
     IiEmitOpcode 0xDA
.op: IiAbortIfNot Operand1,ST0
     IiSwap Operand1,Operand2
     RET
.STi.m16:
     IiEmitOpcode 0xDE
     JMP .op:
 ENDP IifFIADD::

↑ FIMUL

FP Multiply Integer

Description

FIMUL

Category

x87fpu,arith

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /1 | 0xDE ^MF /1

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3580

IifFIMUL:: PROC
     IiModRM /1
     JMP IifFIADD.rm:
 ENDP IifFIMUL::

↑ FICOM

FP Compare Integer

Description

FICOM

Category

x87fpu,compar

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /2 | 0xDE ^MF /2

Flags

modified:0123, defined:0123

Tested by

t3580

IifFICOM:: PROC
    IiModRM /2
    JMP IifFIADD.rm:
 ENDP IifFICOM::

↑ FICOMP

FP Compare Integer and Pop

Description

FICOMP

Category

x87fpu,compar

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /3 | 0xDE ^MF /3

Flags

modified:0123, defined:0123

Tested by

t3580

IifFICOMP:: PROC
     IiModRM /3
     JMP IifFIADD.rm:
 ENDP IifFICOMP::

↑ FISUB

FP Subtract Integer

Description

FISUB

Category

x87fpu,arith

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /4 | 0xDE ^MF /4

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3580

IifFISUB:: PROC
    IiModRM /4
    JMP IifFIADD.rm:
 ENDP IifFISUB::

↑ FISUBR

FP Reverse Subtract Integer

Description

FISUBR

Category

x87fpu,arith

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /5 | 0xDE ^MF /5

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3580

IifFISUBR:: PROC
    IiModRM /5
    JMP IifFIADD.rm:
 ENDP IifFISUBR::

↑ FIDIV

FP Divide Integer

Description

FIDIV

Category

x87fpu,arith

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /6 | 0xDE ^MF /6

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3580

IifFIDIV:: PROC
     IiModRM /6
     JMP IifFIADD.rm:
 ENDP IifFIDIV::

↑ FIDIVR

FP Reverse Divide Integer

Description

FIDIVR

Category

x87fpu,arith

Operands

ST,Mdi | ST,Mwi

Opcode

0xDA ^mF /7 | 0xDE ^MF /7

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3580

IifFIDIVR:: PROC
     IiModRM /7
     JMP IifFIADD.rm:
 ENDP IifFIDIVR::

↑ IifFADDP

IifFADDP is a common handler for FP instructions with opcode 0xDE which calculate the result of mathematic operation with two numbers and then pop the FP stack.
The first operand is always in ST0 (it will be discarded after pop), the second operand (destination) is in any FP register.

Description

FADDP

Reference

FopP STi,ST0	STi := STi op ST0, then POP
FopP€ STi	STi := STi op ST0, then POP
FopR	STi := STi op ST0, then POP

See also

FADDP, FMULP, FCOMP5, FSUBP, FSUBRP, FDIVP, FDIVRP

Opcode

0xDE /0 | 0xDEC1 /0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3555

IifFADDP:: PROC
    IiModRM /0
.rm:IiRequire 086,FPU
    IiEmitOpcode 0xDE
    IiOpEn M
    IiDispatchFormat none, STi:, STi.STi
.STi.STi:IiAbortIfNot Operand2, ST0
.none:
    IiAssumeEmpty Operand1, ST1
.STi:RET
 ENDP IifFADDP::

↑ FMULP

Multiply and Pop

Description

FMULP

Category

x87fpu,arith

Operands

EST,ST | ST1,ST

Opcode

0xDE /1 | 0xDEC9 /1

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3555

IifFMULP:: PROC
     IiModRM /1
     JMP IifFADDP.rm:
 ENDP IifFMULP::

↑ FCOMP5

FP Compare and Pop, undocumented

Category

x87fpu,arith

Operands

EST,ST | ST1,ST

Opcode

0xDE /2

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3555

IifFCOMP5:: PROC
     IiRequire UNDOC
     IiModRM /2
     JMP IifFADDP.rm:
 ENDP IifFCOMP5::

↑ FSUBRP

Reverse Subtract and Pop

Description

FSUBRP

Category

x87fpu,arith

Operands

EST,ST | ST1,ST

Opcode

0xDE /4 | 0xDEE1 /4

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3555

IifFSUBRP:: PROC
    IiModRM /4
    JMP IifFADDP.rm:
 ENDP IifFSUBRP::

↑ FSUBP

Subtract and Pop

Description

FSUBP

Category

x87fpu,arith

Operands

EST,ST | ST1,ST

Opcode

0xDE /5 | 0xDEE9 /5

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3555

IifFSUBP:: PROC
    IiModRM /5
    JMP IifFADDP.rm:
 ENDP IifFSUBP::

↑ FDIVRP

Reverse Divide and Pop

Description

FDIVRP

Category

x87fpu,arith

Operands

EST,ST | ST1,ST

Opcode

0xDE /6 | 0xDEF1 /6

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3555

IifFDIVRP:: PROC
     IiModRM /6
     JMP IifFADDP.rm:
 ENDP IifFDIVRP::

↑ FDIVP

Divide and Pop

Description

FDIVP

Category

x87fpu,arith

Operands

EST,ST | ST1,ST

Opcode

0xDE /7 | 0xDEF9 /7

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3555

IifFDIVP:: PROC
     IiModRM /7
     JMP IifFADDP.rm:
 ENDP IifFDIVP::

↑ FNOP

FP no operation

Description

FNOP

Comment

IifFNOP and similar area FP unary instructions with opcode 0xD9 which use implicit one or two registers from the top of FPU stack (ST0, sometimes ST1 or condition flags C0..C3.).
In €ASM they may be specified with operand ST0 or operands may be omitted.

Reference

Fop	destination and source is ST0
Fop€ ST0	destination and source is ST0

See also

FNOP, FCHS, FABS, FTST, FXAM, FTSTP, FLD1, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, FLDZ, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSQRT, FSINCOS, FRNDINT, FSCALE, FSIN, FCOS.

Opcode

0xD9D0

Flags

modified:0123, undefined:0123

Tested by

t3510

IifFNOP:: PROC
     MOV CL,0xD0
.op: IiRequire 086,FPU
     IiEmitOpcode 0xD9,ECX     
     IiDispatchFormat none, STi:
.STi:IiAbortIfNot Operand1, ST0
.none:RET
 ENDP IifFNOP::

↑ FCHS

FP Change Sign

Description

FCHS

Category

x87fpu,arith

Operands

ST

Opcode

0xD9E0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3510

IifFCHS:: PROC
    MOV CL,0xE0
    JMP IifFNOP.op:
 ENDP IifFCHS::

↑ FABS

FP Absolute Value

Description

FABS

Category

x87fpu,arith

Operands

ST

Opcode

0xD9E1

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3510

IifFABS:: PROC
    MOV CL,0xE1
    JMP IifFNOP.op:
 ENDP IifFABS::

↑ FTST

FP Test

Description

FTST

Category

x87fpu,compar

Operands

ST

Opcode

0xD9E4

Flags

modified:0123, defined:0123

Tested by

t3510

IifFTST:: PROC
    MOV CL,0xE4
    JMP IifFNOP.op:
    ENDP IifFTST::

↑ FXAM

FP Examine

Description

FXAM

Category

x87fpu

Operands

ST

Opcode

0xD9E5

Flags

modified:0123, defined:0123

Tested by

t3510

IifFXAM:: PROC
    MOV CL,0xE5
    JMP IifFNOP.op:
 ENDP IifFXAM::

↑ FTSTP

 

Opcode

0xD9E6

Tested by

t3510

IifFTSTP:: PROC
    IiRequire CYRIX
    MOV CL,0xE6
    JMP IifFNOP.op:
    ENDP IifFTSTP::

↑ FLD1

FP Load Constant +1.0

Description

FLD1

Category

x87fpu,ldconst

Operands

ST

Opcode

0xD9E8 /5

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3512

IifFLD1:: PROC
    MOV CL,0xE8
    JMP IifFNOP.op:
 ENDP IifFLD1::

↑ FLDL2T

FP Load Constant log₂10

Description

FLDL2T

Category

x87fpu,ldconst

Operands

ST

Opcode

0xD9E9

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3512

IifFLDL2T:: PROC
    MOV CL,0xE9
    JMP IifFNOP.op:
    ENDP IifFLDL2T::

↑ FLDL2E

FP Load Constant log₂e

Description

FLDL2E

Category

x87fpu,ldconst

Operands

ST

Opcode

0xD9EA

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3512

IifFLDL2E:: PROC
    MOV CL,0xEA
    JMP IifFNOP.op:
    ENDP IifFLDL2E::

↑ FLDPI

FP Load Constant π

Description

FLDPI

Category

x87fpu,ldconst

Operands

ST

Opcode

0xD9EB

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3512

IifFLDPI:: PROC
    MOV CL,0xEB
    JMP IifFNOP.op:
    ENDP IifFLDPI::

↑ FLDLG2

FP Load Constant log₁₀2

Description

FLDLG2

Category

x87fpu,ldconst

Operands

ST

Opcode

0xD9EC

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3512

IifFLDLG2:: PROC
    MOV CL,0xEC
    JMP IifFNOP.op:
    ENDP IifFLDLG2::

↑ FLDLN2

FP Load Constant log_e2

Description

FLDLN2

Category

x87fpu,ldconst

Operands

ST

Opcode

0xD9ED

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3512

IifFLDLN2:: PROC
    MOV CL,0xED
    JMP IifFNOP.op:
    ENDP IifFLDLN2::

↑ FLDZ

FP Load Constant +0.0

Description

FLDZ

Category

x87fpu,ldconst

Operands

ST

Opcode

0xD9EE

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3512

IifFLDZ:: PROC
    MOV CL,0xEE
    JMP IifFNOP.op:
    ENDP IifFLDZ::

↑ F2XM1

FP Compute 2^x-1

Description

F2XM1

Category

x87fpu,trans

Operands

ST

Opcode

0xD9F0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3515

IifF2XM1:: PROC
    MOV CL,0xF0
    JMP IifFNOP.op:
 ENDP IifF2XM1::

↑ FYL2X

FP Compute Fp Y * Log₂ X

Description

FYL2X

Category

x87fpu,trans

Operands

ST1,ST

Opcode

0xD9F1

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3515

IifFYL2X:: PROC
    MOV CL,0xF1
    JMP IifFNOP.op:
 ENDP IifFYL2X::

↑ FPTAN

FP Partial Tangent

Description

FPTAN

Category

x87fpu,trans

Operands

ST

Opcode

0xD9F2

Flags

modified:0123, defined:.12., undefined:0..3

Tested by

t3515

IifFPTAN:: PROC
    MOV CL,0xF2
    JMP IifFNOP.op:
 ENDP IifFPTAN::

↑ FPATAN

FP Partial Arctangent and Pop

Description

FPATAN

Category

x87fpu,trans

Operands

ST1,ST

Opcode

0xD9F3

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3515

IifFPATAN:: PROC
    MOV CL,0xF3
    JMP IifFNOP.op:
 ENDP IifFPATAN::

↑ FXTRACT

FP Extract Exponent and Significand

Description

FXTRACT

Category

x87fpu,arith

Operands

ST

Opcode

0xD9F4

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3515

IifFXTRACT:: PROC
    MOV CL,0xF4
    JMP IifFNOP.op:
    RET
 ENDP IifFXTRACT::

↑ FPREM1

IEEE Partial Remainder

Description

FPREM1

Category

x87fpu,arith

Operands

ST,ST1

Opcode

0xD9F5

Flags

modified:0123, defined:0123

Tested by

t3515

IifFPREM1:: PROC
    MOV CL,0xF5
    JMP IifFNOP.op:
 ENDP IifFPREM1::

↑ FDECSTP

Decrement FPU Stack-Top Pointer

Description

FDECSTP

Category

x87fpu,control

Opcode

0xD9F6

Flags

modified:0123, defined:.1.., undefined:0.23, values:.0..

Tested by

t3515

IifFDECSTP:: PROC
    MOV CL,0xF6
    JMP IifFNOP.op:
 ENDP IifFDECSTP::

↑ FINCSTP

Increment FPU Stack-Top Pointer

Description

FINCSTP

Category

x87fpu,control

Opcode

0xD9F7

Flags

modified:0123, defined:.1.., undefined:0.23, values:.0..

Tested by

t3515

IifFINCSTP:: PROC
    MOV CL,0xF7
    JMP IifFNOP.op:
 ENDP IifFINCSTP::

↑ FPREM

FP Partial Remainder (for compatibility with i8087 and i287)

Description

FPREM

Category

x87fpu,arith

Operands

ST,ST1

Opcode

0xD9F8

Flags

modified:0123, defined:0123

Tested by

t3520

IifFPREM:: PROC
    MOV CL,0xF8
    JMP IifFNOP.op:
 ENDP IifFPREM::

↑ FYL2XP1

FP Compute Fp Y * Log₂ (X + 1) & Pop

Description

FYL2XP1

Category

x87fpu,trans

Operands

ST1,ST

Opcode

0xD9F9

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3520

IifFYL2XP1:: PROC
    MOV CL,0xF9
    JMP IifFNOP.op:
    RET
 ENDP IifFYL2XP1::

↑ FSQRT

FP Square Root

Description

FSQRT

Category

x87fpu,arith

Operands

ST

Opcode

0xD9FA

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3520

IifFSQRT:: PROC
    MOV CL,0xFA
    JMP IifFNOP.op:
 ENDP IifFSQRT::

↑ FSINCOS

FP Sine and Cosine

Description

FSINCOS

Category

x87fpu,trans

Operands

ST

Opcode

0xD9FB

Flags

modified:0123, defined:.12., undefined:0..3

Tested by

t3520

IifFSINCOS:: PROC
    MOV CL,0xFB
    JMP IifFNOP.op:
 ENDP IifFSINCOS::

↑ FRNDINT

FP Round to Integer

Description

FRNDINT

Category

x87fpu,arith

Operands

ST

Opcode

0xD9FC

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3520

IifFRNDINT:: PROC
    MOV CL,0xFC
    JMP IifFNOP.op:
    ENDP IifFRNDINT::

↑ FSCALE

FP Scale

Description

FSCALE

Category

x87fpu,arith

Operands

ST,ST1

Opcode

0xD9FD

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3520

IifFSCALE:: PROC
    MOV CL,0xFD
    JMP IifFNOP.op:
 ENDP IifFSCALE::

↑ FSIN

FP Sine

Description

FSIN

Category

x87fpu,trans

Operands

ST

Opcode

0xD9FE

Flags

modified:0123, defined:.12., undefined:0..3

Tested by

t3520

IifFSIN:: PROC
    MOV CL,0xFE
    JMP IifFNOP.op:
 ENDP IifFSIN::

↑ FCOS

FP Cosine

Description

FCOS

Category

x87fpu,trans

Operands

ST

Opcode

0xD9FF

Flags

modified:0123, defined:.12., undefined:0..3

Tested by

t3520

IifFCOS:: PROC
    MOV CL,0xFF
    JMP IifFNOP.op:
 ENDP IifFCOS::

↑ FRICHOP

 

Operands

-

Opcode

0xDDFC

Tested by

t3510

IifFRICHOP:: PROC
    IiRequire FPU,CYRIX
    IiEmitOpcode 0xDD,0xFC
    IiDispatchFormat none
.none:RET    
    ENDP IifFRICHOP::

↑ FRINT2

 

Operands

-

Opcode

0xDBFC

Tested by

t3510

IifFRINT2:: PROC
    IiRequire FPU,CYRIX
    IiEmitOpcode 0xDB,0xFC
    IiDispatchFormat none
.none:RET    
    ENDP IifFRINT2::

↑ FRINEAR

 

Operands

-

Opcode

0xDDFC

Tested by

t3510

IifFRINEAR:: PROC
    IiRequire FPU,CYRIX
    IiEmitOpcode 0xDF,0xFC
    IiDispatchFormat none
.none:RET    
    ENDP IifFRINEAR::

↑ FLD

Load Floating Point Value

Description

FLD

Category

x87fpu,datamov

Operands

ST,ESsr | ST,Mer | ST,Mdr

Opcode

0xD9 ^mf /0 | 0xDB /5 | 0xDD ^Mf /0

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3585

IifFLD:: PROC
     IiRequire 086,FPU
     IiOpEn M
     IiDataSize FloatingPoint=ON
     IiDispatchFormat m32,m64,m80,STi:,STi.m32,STi.m64,STi.m80,STi.STi
.STi:
.m32:IiEmitOpcode 0xD9
     IiModRM /0
     RET
.m64:IiEmitOpcode 0xDD
     IiModRM /0
     RET
.m80:IiEmitOpcode 0xDB
     IiModRM /5
     RET
.STi.STi:
.STi.m32:
     IiEmitOpcode 0xD9
 .d0:IiModRM /0
 .sw:IiAbortIfNot Operand1, ST0
     IiSwap Operand1,Operand2
     RET
.STi.m64:
     IiEmitOpcode 0xDD
     JMP .d0:
.STi.m80:
     IiEmitOpcode 0xDB
     IiModRM /5
     JMP .sw:
 ENDP IifFLD::

↑ FXCH

Exchange FP Register contents

Description

FXCH

Reference

Finstr ST0, STi	exchange ST0 with STi
Finstr STi, ST0	exchange STi with ST0
Finstr STi	exchange STi with ST0
Finstr	exchange ST1 with ST0

Category

x87fpu,datamov

Operands

ST,EST | ST,ST1

Opcode

0xD9 ^mf /1 | 0xD9C9 /1

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3560

IifFXCH:: PROC
     IiEmitOpcode 0xD9
.op: IiRequire 086,FPU
     IiOpEn M
     IiModRM /1
     IiDispatchFormat none,STi:,STi.STi
.STi.STi:
     IiAbortIfNotST0
     JC .STi: ; If Operand1 is not ST0.
     IiSwap Operand1,Operand2
.none:IiAssumeEmpty Operand1, ST1
.STi:RET
 ENDP IifFXCH::

↑ FXCH4

Exchange Register Contents (alias FXCH)

Category

x87fpu,datamov

Operands

ST,EST | ST,EST

Opcode

0xDD /1 | 0xDD /1

Flags

modified:0123, defined:.1.., undefined:0.23

CPU

00-02

Documented

D¹⁴

Tested by

t3560

IifFXCH4:: PROC
    IiRequire UNDOC
    IiEmitOpcode 0xDD
    JMP IifFXCH.op:
 ENDP IifFXCH4::

↑ FXCH7

Exchange Register Contents (alias FXCH)

Category

x87fpu,datamov

Operands

ST,EST | ST,EST

Opcode

0xDF /1 | 0xDF /1

Flags

modified:0123, defined:.1.., undefined:0.23

CPU

00-02

Documented

D¹⁴

Tested by

t3560

IifFXCH7:: PROC
    IiRequire UNDOC
    IiEmitOpcode 0xDF
    JMP IifFXCH.op:
 ENDP IifFXCH7::

↑ FBLD

FP Load Binary Coded Decimal

Description

FBLD

Category

x87fpu,datamov

Operands

ST,Mbcd

Opcode

0xDF /4

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3595

IifFBLD:: PROC
    IiRequire 086,FPU
    IiEmitOpcode 0xDF
    IiEncoding DATA=TBYTE
    IiOpEn M
    IiModRM /4
    IiDispatchFormat mem, STi.mem
.STi.mem:
    IiAbortIfNot Operand1, ST0
    IiSwap Operand1,Operand2
.mem:RET
 ENDP IifFBLD::

↑ FBSTP

FP Store to BCD Integer and Pop

Description

FBSTP

Category

x87fpu,datamov

Operands

Mbcd,ST

Opcode

0xDF /6

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3595

IifFBSTP:: PROC
     IiRequire 086,FPU
     IiEmitOpcode 0xDF
     IiEncoding DATA=TBYTE
     IiOpEn M
     IiModRM /6
     IiDispatchFormat mem, mem.STi
.mem.STi:
     IiAbortIfNot Operand2, ST0
.mem:RET
 ENDP IifFBSTP::

↑ FILD

FP Load Integer

Description

FILD

Category

x87fpu,datamov

Operands

ST,Mdi | ST,Mwi | ST,Mqi

Opcode

0xDB ^mF /0 | 0xDF ^MF /0 | 0xDF /5

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3585

IifFILD:: PROC
     IiRequire 086,FPU
     IiDataSize FloatingPoint=ON
     IiOpEn M
     IiDispatchFormat m32, m16, m64, STi.m32, STi.m16, STi.m64
.m16:IiEmitOpcode 0xDF
.d0: IiModRM /0
     RET
.m32:IiEmitOpcode 0xDB
     JMP .d0:
.m64:IiEmitOpcode 0xDF
     IiModRM /5
     RET
.STi.m16:
     CALL .m16:
.sw: IiAbortIfNot Operand1, ST0
     IiSwap Operand1,Operand2
     RET
.STi.m32:
     CALL .m32:
     JMP .sw:
.STi.m64:
     CALL .m64:
     JMP .sw:
 ENDP IifFILD::

↑ FISTTP

FP Store Integer with Truncation and Pop

Description

FISTTP

Category

sse3,x87fpu,conver

Operands

Mdi,ST | Mqi,ST | Mwi,ST

Opcode

0xDB ^mF /1 | 0xDD /1 | 0xDF ^MF /1

Flags

modified:0123, defined:.1.., undefined:0.23, values:.0..

CPU

P4++

Tested by

t3590

IifFISTTP:: PROC
     IiRequire 086,FPU
     IiOpEn M
     IiModRM /1
     IiDataSize FloatingPoint=ON
     IiAssumeEmpty Operand2,ST0
     IiAbortIfNot  Operand2,ST0
     IiDispatchFormat m32,m16,m64, m32.STi, m16.STi, m64.STi
.m16.STi:
.m16:IiEmitOpcode 0xDF
     RET
.m32.STi:
.m32:IiEmitOpcode 0xDB
     RET
.m64.STi:
.m64:IiEmitOpcode 0xDD
     RET
 ENDP IifFISTTP::

↑ FIST

FP Store Integer

Description

FIST

Category

x87fpu,datamov

Operands

Mdi,ST | Mwi,ST

Opcode

0xDB ^mF /2 | 0xDF ^MF /2

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3590

IifFIST:: PROC
     IiRequire 086,FPU
     IiOpEn M
     IiModRM /2
     IiDataSize FloatingPoint=ON
     IiAssumeEmpty Operand2,ST0
     IiAbortIfNot  Operand2,ST0
     IiDispatchFormat m32,m16, m32.STi, m16.STi
.m16.STi:
.m16:IiEmitOpcode 0xDF
     RET
.m32.STi:
.m32:IiEmitOpcode 0xDB
     RET
 ENDP IifFIST::

↑ FISTP

FP Store Integer and Pop

Description

FISTP

Category

x87fpu,datamov

Operands

Mdi,ST | Mwi,ST | Mqi,ST

Opcode

0xDB ^mF /3 | 0xDF ^MF /3 | 0xDF /7

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3590

IifFISTP:: PROC
     IiRequire 086,FPU
     IiOpEn M
     IiDataSize FloatingPoint=ON
     IiAssumeEmpty Operand2,ST0
     IiAbortIfNot  Operand2,ST0
     IiDispatchFormat m32,m16,m64, m32.STi, m16.STi, m64.STi
.m16.STi:
.m16:IiEmitOpcode 0xDF
     IiModRM /3
     RET
.m32.STi:
.m32:IiEmitOpcode 0xDB
     IiModRM /3
     RET
.m64.STi:
.m64:IiEmitOpcode 0xDF
     IiModRM /7
     RET
 ENDP IifFISTP::

↑ FST

Store Floating Point Value

Description

FST

Category

x87fpu,datamov

Operands

Msr,ST | Mdr,ST | ST,EST

Opcode

0xD9 ^mf /2 | 0xDD ^Mf /2 | 0xDD /2

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3540

IifFST:: PROC
     IiRequire 086,FPU
     IiDataSize Operand1,FloatingPoint=ON
     IiAssumeEmpty Operand2, ST0 ; Two-operand version may have optional 2nd operand ST0.
     IiAbortIfNot  Operand2, ST0
     IiOpEn M
     IiModRM /2
     IiDispatchFormat STi:,m32,m64,STi.STi,m32.STi,m64.STi
.m32.STi:     
.m32:IiEmitOpcode 0xD9
     RET
.STi.STi:
.STi:     
.m64.STi:     
.m64:IiEmitOpcode 0xDD
     RET
   ENDP IifFST::

↑ FSTP

Store Floating Point Value and Pop

Description

FSTP

Category

x87fpu,datamov

Operands

Msr,ST | Mer,ST | Mdr,ST | ST,EST

Opcode

0xD9 ^mf /3 | 0xDB /7 | 0xDD ^Mf /3 | 0xDD /3

Flags

modified:0123, defined:.1.., undefined:0.23

Tested by

t3540

IifFSTP:: PROC
     IiRequire 086,FPU
     IiDataSize Operand1,FloatingPoint=ON
     IiAssumeEmpty Operand2, ST0 ; Two-operand version may have optional 2nd operand ST0.
     IiAbortIfNot  Operand2, ST0
     IiOpEn M
     IiDispatchFormat STi:,m32,m64,m80,STi.STi,m32.STi,m64.STi,m80.STi
.STi.STi:
.STi:
.m64.STi:
.m64:IiEmitOpcode 0xDD
     IiModRM /3
     RET
.m32.STi:
.m32:IiEmitOpcode 0xD9
     IiModRM /3
     RET
.m80.STi:
.m80:IiEmitOpcode 0xDB
     IiModRM /7
     RET
   ENDP IifFSTP::

↑ FSTP1

Store Floating Point Value and Pop (alias FSTP)

Category

x87fpu,datamov

Operands

EST,ST | EST,ST

Opcode

0xD9 /3 | 0xD9 /3

Flags

modified:0123, defined:.1.., undefined:0.23

CPU

00-02

Documented

D⁸

Tested by

t3540

IifFSTP1:: PROC
    IiRequire FPU,UNDOC
    IiEmitOpcode 0xD9
    IiOpEn M
    IiModRM /3
    IiDispatchFormat STi 
.STi:RET
 ENDP IifFSTP1::

↑ FSTP8

Store Floating Point Value and Pop (alias FSTP)

Category

x87fpu,datamov

Operands

EST,ST | EST,ST

Opcode

0xDF /2 | 0xDF /2

Flags

modified:0123, defined:.1.., undefined:0.23

CPU

00-02

Documented

D⁸

Tested by

t3540

IifFSTP8:: PROC
    IiRequire FPU,UNDOC
    IiEmitOpcode 0xDF
    IiOpEn M
    IiModRM /2
    IiDispatchFormat STi 
.STi:RET
 ENDP IifFSTP8::

↑ FSTP9

Store Floating Point Value and Pop (alias FSTP)

Category

x87fpu,datamov

Operands

EST,ST | EST,ST

Opcode

0xDF /3 | 0xDF /3

Flags

modified:0123, defined:.1.., undefined:0.23

CPU

00-02

Documented

D⁸

Tested by

t3540

IifFSTP9:: PROC
    IiRequire FPU,UNDOC
    IiEmitOpcode 0xDF
    IiOpEn M
    IiModRM /3
    IiDispatchFormat STi 
.STi:RET
 ENDP IifFSTP9::

↑ FUCOM

Unordered Compare Floating Point Values

Description

FUCOM

Reference

FCOM ST0, STi	compare ST0 with STi
FCOM STi	compare ST0 with STi
FCOM	compare ST0 with ST1

Category

x87fpu,compar

Operands

ST,EST | ST,ST1

Opcode

0xDD /4 | 0xDDE1 /4

Flags

modified:0123, defined:0123

CPU

03+

Tested by

t3535

IifFUCOM:: PROC
    IiModRM /4
.rm:IiRequire 386,FPU
    IiEmitOpcode 0xDD
    IiOpEn M
    IiDispatchFormat none,STi:,STi.STi
.STi.STi:
    IiAbortIfNot Operand1, ST0
    IiSwap Operand1,Operand2
.none:IiAssumeEmpty Operand1, ST1
.STi:RET
 ENDP IifFUCOM::

↑ FUCOMP

Unordered Compare Floating Point Values and Pop

Description

FUCOMP

Reference

FUCOMP ST0, STi	compare ST0 with STi
FUCOMP STi	compare ST0 with STi
FUCOMP	compare ST0 with ST1

Category

x87fpu,compar

Operands

ST,EST | ST,ST1

Opcode

0xDD /5 | 0xDDE9 /5

Flags

modified:0123, defined:0123

CPU

03+

Tested by

t3535

IifFUCOMP:: PROC
    IiModRM /5
    JMP IifFUCOM.rm:
 ENDP IifFUCOMP::

↑ FUCOMPP

Unordered Compare Floating Point Values ST0,ST1 and Pop Twice

Description

FUCOMPP

Reference

FCOMPP ST0, ST1	compare ST0 with ST1
FCOMPP ST1	compare ST0 with ST1
FCOMPP	compare ST0 with ST1

Category

x87fpu,compar

Operands

ST,ST1

Opcode

0xDAE9 /5

Flags

modified:0123, defined:0123

CPU

03+

Tested by

t3535

IifFUCOMPP:: PROC
    IiEmitOpcode 0xDA,0xE9
.op:IiRequire 386,FPU
    IiDispatchFormat none,STi:,STi.STi
.STi:IiAbortIfNot Operand1, ST1
.none:RET
.STi.STi:
    IiAbortIfNot Operand2, ST1
    IiAbortIfNot Operand1, ST0
    RET
 ENDP IifFUCOMPP::

↑ FCOMPP

Compare Floating Point Values ST0,ST1 and Pop Twice

Description

FCOMPP

Reference

FCOMPP ST0, ST1	compare ST0 with ST1
FCOMPP ST1	compare ST0 with ST1
FCOMPP	compare ST0 with ST1

Category

x87fpu,compar

Operands

ST,ST1

Opcode

0xDED9 /3

Flags

modified:0123, defined:0123

Tested by

t3535

IifFCOMPP:: PROC
    IiEmitOpcode 0xDE,0xD9
    JMP IifFUCOMPP.op:
 ENDP IifFCOMPP::

↑ FFREE

Free Floating-Point Register

Description

FFREE

Category

x87fpu,control

Operands

EST

Opcode

0xDD /0

Flags

modified:0123, undefined:0123

Tested by

t3500

IifFFREE:: PROC
     IiRequire 086,FPU
     IiEmitOpcode 0xDD
.op: IiOpEn M
     IiModRM /0
     IiDispatchFormat STi:
.STi:RET
 ENDP IifFFREE::

↑ FFREEP

Free Floating-Point Register and pop (undocumented by Intel)

Opcode

0xDF /0

CPU

AMD, Geode

Documented

gcc

Tested by

t3500

IifFFREEP:: PROC
    IiRequire 586,FPU,UNDOC
    IiEmitOpcode 0xDF
    JMP IifFFREE.op:
 ENDP IifFFREEP::

↑ FLDENV

Load x87 FPU Environment

Description

FLDENV

Category

x87fpu,control

Operands

Me

Opcode

0xD9 /4

Flags

modified:0123, defined:0123

Tested by

t3565

IifFLDENV:: PROC
     IiRequire 086,FPU
     IiEmitOpcode 0xD9
     IiOpEn M
     IiModRM /4
     IiDispatchFormat mem
.mem:RET
 ENDP IifFLDENV::

↑ FLDCW

Load x87 FPU Control Word

Description

FLDCW

Category

x87fpu,control

Operands

Mw

Opcode

0xD9 /5

Flags

modified:0123, undefined:0123

Tested by

t3565

IifFLDCW:: PROC
     IiRequire 086,FPU
     IiEmitOpcode 0xD9
     IiEncoding DATA=WORD
     IiOpEn M
     IiModRM /5
     IiDispatchFormat mem
.mem:RET
 ENDP IifFLDCW::

↑ FNSTENV Nowait STore FPU ENVironment

IifFNSTENV:: PROC
     IiRequire 086,FPU
     IiEmitOpcode 0xD9
     IiOpEn M
     IiModRM /6
     IiDispatchFormat mem
.mem:RET
 ENDP IifFNSTENV::

↑ FSTENV

Store FPU Environment

Description

FSTENV

Category

x87fpu,control

Operands

Me

Opcode

0x9BD9 /6

Flags

modified:0123, undefined:0123

Tested by

t3565

IifFSTENV:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNSTENV
 ENDP IifFSTENV::

↑ FNSTCW

Nowait Store FPU Control Word

Description

FNSTCW

Category

x87fpu,control

Operands

Mw

Opcode

0xD9 /7

Flags

modified:0123, undefined:0123

Tested by

t3565

IifFNSTCW:: PROC
     IiRequire 086,FPU
     IiEmitOpcode 0xD9
     IiEncoding DATA=WORD
     IiOpEn M
     IiModRM /7
     IiDispatchFormat mem
.mem:RET
 ENDP IifFNSTCW::

↑ FSTCW

Store x87 FPU Control Word

Description

FSTCW

Category

x87fpu,control

Operands

Mw

Opcode

0x9BD9 /7

Flags

modified:0123, undefined:0123

Tested by

t3565

IifFSTCW:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNSTCW
 ENDP IifFSTCW::

↑ FNSTSW

Nowait Store FPU Status Word

Description

FNSTSW

Category

x87fpu,control

Operands

Mw | AX

Opcode

0xDD /7 | 0xDFE0 /4

Flags

modified:0123, undefined:0123

Tested by

t3565

IifFNSTSW:: PROC
    IiRequire 086,FPU
    IiEncoding DATA=WORD
    IiDispatchFormat mem,r16
.r16:IiAbortIfNot Operand1,AX
    IiEmitOpcode 0xDF,0xE0
    IiRequire 286
    RET
.mem:IiEmitOpcode 0xDD
    IiOpEn M
    IiModRM /7
    RET
 ENDP IifFNSTSW::

↑ FSTSW

Store FPU Status Word

Description

FSTSW

Category

x87fpu,control

Operands

Mw | AX

Opcode

0x9BDD /7 | 0x9BDFE0 /4

Flags

modified:0123, undefined:0123

Tested by

t3565

IifFSTSW:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNSTSW
 ENDP IifFSTSW::

↑ FSTSG

?

Operands

AX

Opcode

0xDFE2

CPU

80387SL

Documented

sandpile

Tested by

t3565

IifFSTSG:: PROC
    IiRequire 386,FPU,UNDOC
    IiEmitOpcode 0xDF,0xE2
    IiAbortIfNot Operand1, AX
    IiDispatchFormat r16 
.r16:RET
 ENDP IifFSTSG::

↑ FSTDW

?

Operands

AX

Opcode

0xDFE1

CPU

80387SL

Documented

sandpile

Tested by

t3565

IifFSTDW:: PROC
    IiRequire 386,FPU,UNDOC
    IiEmitOpcode 0xDF,0xE1
    IiAbortIfNot Operand1, AX
    IiDispatchFormat r16 
.r16:RET
 ENDP IifFSTDW::

↑ FNENI

Nowait Enable NPX Interrupt

Category

x87fpu,control

Opcode

0xDBE0 /4

CPU

00

Tested by

t3505

IifFNENI:: PROC
    IiRequire 086,FPU
    IiEmitOpcode 0xDB,0xE0
    IiDispatchFormat none
.none:RET
 ENDP IifFNENI::

↑ FENI

Enable NPX Interrupt

Category

x87fpu,control

Opcode

0x9BDBE0 /4

CPU

00

Tested by

t3505

IifFENI:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNENI:
 ENDP IifFENI::

↑ FNDISI

Nowait Disable NPX Interrupt

Category

x87fpu,control

Opcode

0xDBE1 /4

CPU

00

Tested by

t3505

IifFNDISI:: PROC
    IiRequire 086,FPU
    IiEmitOpcode 0xDB,0xE1
    IiDispatchFormat none
.none:RET
 ENDP IifFNDISI::

↑ FDISI

Disable NPX Interrupt

Category

x87fpu,control

Opcode

0x9BDBE1 /4

CPU

00

Tested by

t3505

IifFDISI:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNDISI:
 ENDP IifFDISI::

↑ FNCLEX

Nowait Clear Exceptions

Description

FNCLEX

Category

x87fpu,control

Opcode

0xDBE2 /4

Flags

modified:0123, undefined:0123

Tested by

t3505

IifFNCLEX:: PROC
    IiRequire 086,FPU
    IiEmitOpcode 0xDB,0xE2
    IiDispatchFormat none
.none:RET
 ENDP IifFNCLEX::

↑ FCLEX

Clear Exceptions

Description

FCLEX

Category

x87fpu,control

Opcode

0x9BDBE2 /4

Flags

modified:0123, undefined:0123

Tested by

t3505

IifFCLEX:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNCLEX:
 ENDP IifFCLEX::

↑ FNINIT

Initialize Floating-Point Unit

Description

FNINIT

Category

x87fpu,control

Opcode

0xDBE3 /4

Flags

modified:0123, values:0000

Tested by

t3505

IifFNINIT:: PROC
    IiRequire 086,FPU
    IiEmitOpcode 0xDB,0xE3
    IiDispatchFormat none
.none:RET
 ENDP IifFNINIT::

↑ FINIT

Initialize Floating-Point Unit

Description

FINIT

Category

x87fpu,control

Opcode

0x9BDBE3 /4

Flags

modified:0123, values:0000

Tested by

t3505

IifFINIT:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNINIT:
 ENDP IifFINIT::

↑ FNSETPM

Nowait Set Protected Mode

Category

x87fpu,control

Opcode

0xDBE4 /4

CPU

80287

Tested by

t3505

IifFNSETPM:: PROC
    IiRequire 286,FPU,UNDOC
    IiEmitOpcode 0xDB,0xE4
    IiDispatchFormat none
.none:RET
  ENDP IifFNSETPM::

↑ FSETPM

Set Protected Mode

Category

x87fpu,control

Opcode

0x9BDBE4 /4

CPU

02

Tested by

t3505

IifFSETPM:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNSETPM:
  ENDP IifFSETPM::

↑ FRSTPM

FPU reset to real mode

Opcode

0xDBE5 | 0xDBF4

CPU

80287XL

Documented

PCDOSRETRO

Tested by

t3505

IifFRSTPM:: PROC
    IiRequire FPU,PROT,UNDOC
    IiAllowModifier CODE
    IiEmitOpcode 0xDB
    IiDispatchFormat none 
.none:
    IiDispatchCode LONG=.L:
    IiEncoding CODE=SHORT
    IiEmitOpcode 0xE5
    RET
.L: IiEncoding CODE=LONG
    IiEmitOpcode 0xF4
    RET     
 ENDP IifFRSTPM::

↑ FWAIT

Check pending unmasked floating-point exceptions

Description

FWAIT

Category

x87fpu,control

Opcode

0x9B

Flags

modified:0123, undefined:0123

Tested by

t3500

IifFWAIT:: PROC
    IiRequire 086,FPU
    IiEmitOpcode 0x9B
    IiDispatchFormat none
.none:RET
 ENDP IifFWAIT::

↑ WAIT

Check pending unmasked floating-point exceptions

Description

WAIT

Comment

Alias to FWAIT

Category

x87fpu,control

Opcode

0x9B

Flags

modified:0123, undefined:0123

Tested by

t3500

IifWAIT:: PROC
     JMP IifFWAIT
 ENDP IifWAIT::

↑ FNSAVE

Nowait Store x87 FPU State, nowait

Description

FNSAVE

Category

x87fpu,control

Opcode

0xDD /6

Flags

modified:0123, defined:0123, values:0000

Tested by

t3570

IifFNSAVE:: PROC
    IiRequire 086,FPU,MMX
    IiEmitOpcode 0xDD
    IiOpEn M
    IiModRM /6
    IiDispatchFormat mem
.mem:RET
 ENDP IifFNSAVE::

↑ FSAVE

Store x87 FPU State

Description

FSAVE

Category

x87fpu,control

Operands

Mst

Opcode

0x9BDD /6

Flags

modified:0123, defined:0123, values:0000

Tested by

t3570

IifFSAVE:: PROC
    IiEmitOpcode 0x9B
    JMP IifFNSAVE
 ENDP IifFSAVE::

↑ FRSTOR

Restore x87 FPU State

Description

FRSTOR

Category

x87fpu,control

Operands

ST,ST1,ST2,...

Opcode

0xDD /4

Flags

modified:0123, defined:0123

Tested by

t3570

IifFRSTOR:: PROC
    IiRequire 086,FPU,MMX
    IiEmitOpcode 0xDD
    IiOpEn M
    IiModRM /4
    IiDispatchFormat mem
.mem:RET
 ENDP IifFRSTOR::

↑ FXSAVE

Save x87 FPU, MMX, XMM, and MXCSR State

Description

FXSAVE

Category

sm

Operands

Mstx,ST,ST1,... | Mstx,ST,ST1,...

Opcode

0x0FAE /0 | 0x0FAE /0

CPU

P2++

Tested by

t3570

IifFXSAVE:: PROC
    IiRequire 686,FPU,MMX,SSE1
    IiEmitOpcode 0x0F,0xAE
    IiOpEn M
    IiModRM /0
    IiDispatchFormat mem
.mem:RET
 ENDP IifFXSAVE::

↑ FXSAVE64

Fp SAVE x87 & mmx & Xmm state in 64bit mode

Tested by

t3570

IifFXSAVE64:: PROC
    IiRequire X64
    IiEmitPrefix REX.W
    JMP IifFXSAVE
    RET
 ENDP IifFXSAVE64::

↑ FXRSTOR

Restore x87 FPU, MMX, XMM, and MXCSR State

Description

FXRSTOR

Category

sm

Operands

ST,ST1,ST2,... | ST,ST1,ST2,...

Opcode

0x0FAE /1 | 0x0FAE /1

CPU

P2++

Tested by

t3570

IifFXRSTOR:: PROC
    IiRequire 686,FPU,MMX,SSE1
    IiEmitOpcode 0x0F,0xAE
    IiOpEn M
    IiModRM /1
    IiDispatchFormat mem
.mem:RET
 ENDP IifFXRSTOR::

↑ FXRSTOR64

Fp ReSTORe x87 & mmx & Xmm state in64bit mode

Tested by

t3570

IifFXRSTOR64:: PROC
    IiRequire X64
    IiEmitPrefix REX.W
    JMP IifFXRSTOR
   ENDP IifFXRSTOR64::

↑ FMUL4X4

FP multiply 4x4 matrix

Opcode

0xDBF1

CPU

IIT only

Documented

86BUGS.LST

Tested by

t3575

IifFMUL4X4:: PROC
    MOV CL,0xF1
.op:IiRequire FPU,UNDOC
    IiEmitOpcode 0xDB,ECX
    IiDispatchFormat none 
.none:RET    
 ENDP IifFMUL4X4::

↑ F4X4

Alias to FMUL4X4

Operands

-

Opcode

0xDBF1

CPU

IIT only

Documented

sandpile

Tested by

t3575

IifF4X4:: PROC
    JMP IifFMUL4X4:
 ENDP IifF4X4::

↑ FSBP0

Select Bank 0 for FMUL4X4

Opcode

0xDBE8

CPU

IIT only

Documented

86BUGS.LST

Tested by

t3575

IifFSBP0:: PROC
    MOV CL,0xE8
    JMP IifFMUL4X4.op:
 ENDP IifFSBP0::

↑ FSBP1

Select Bank 1 for FMUL4X4

Operands

-

Opcode

0xDBEB

CPU

IIT only

Documented

86BUGS.LST

Tested by

t3575

IifFSBP1:: PROC
    MOV CL,0xEB
    JMP IifFMUL4X4.op:
 ENDP IifFSBP1::

↑ FSBP2

Select Bank 2 for FMUL4X4

Operands

-

Opcode

0xDBEA

CPU

IIT only

Documented

86BUGS.LST

Tested by

t3575

IifFSBP2:: PROC
    MOV CL,0xEA
    JMP IifFMUL4X4.op:
 ENDP IifFSBP2::

↑ FSBP3

Select Bank 3 for FMUL4X4

Operands

-

Opcode

0xDBE9

CPU

IIT only

Documented

86BUGS.LST

Tested by

t3575

IifFSBP3:: PROC
    MOV CL,0xE9
    JMP IifFMUL4X4.op:
 ENDP IifFSBP3::

  ENDPROGRAM iif