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iix.htm
Enumerations
IizList
Instruction groups
IizGroupVADDPD
IizGroupVADDPS
IizGroupVADDSD
IizGroupVADDSS
IizGroupVMINPD
IizGroupVMINPS
IizGroupVMINSD
IizGroupVMINSS
Instruction handlers
VADDPD VADDPS VADDSD VADDSS VADDSUBPD VADDSUBPS VALIGND VALIGNQ VBLENDMPD VBLENDMPS VBROADCASTF128 VBROADCASTF32X2 VBROADCASTF32X4 VBROADCASTF32X8 VBROADCASTF64X2 VBROADCASTF64X4 VBROADCASTI128 VBROADCASTI32X2 VBROADCASTI32X4 VBROADCASTI32X8 VBROADCASTI64X2 VBROADCASTI64X4 VBROADCASTSD VBROADCASTSS VCMPEQPD VCMPEQPS VCMPEQSD VCMPEQSS VCMPEQ_OQPD VCMPEQ_OQPS VCMPEQ_OQSD VCMPEQ_OQSS VCMPEQ_OSPD VCMPEQ_OSPS VCMPEQ_OSSD VCMPEQ_OSSS VCMPEQ_UQPD VCMPEQ_UQPS VCMPEQ_UQSD VCMPEQ_UQSS VCMPEQ_USPD VCMPEQ_USPS VCMPEQ_USSD VCMPEQ_USSS VCMPFALSEPD VCMPFALSEPS VCMPFALSESD VCMPFALSESS VCMPFALSE_OQPD VCMPFALSE_OQPS VCMPFALSE_OQSD VCMPFALSE_OQSS VCMPFALSE_OSPD VCMPFALSE_OSPS VCMPFALSE_OSSD VCMPFALSE_OSSS VCMPGEPD VCMPGEPS VCMPGESD VCMPGESS VCMPGE_OQPD VCMPGE_OQPS VCMPGE_OQSD VCMPGE_OQSS VCMPGE_OSPD VCMPGE_OSPS VCMPGE_OSSD VCMPGE_OSSS VCMPGTPD VCMPGTPS VCMPGTSD VCMPGTSS VCMPGT_OQPD VCMPGT_OQPS VCMPGT_OQSD VCMPGT_OQSS VCMPGT_OSPD VCMPGT_OSPS VCMPGT_OSSD VCMPGT_OSSS VCMPLEPD VCMPLEPS VCMPLESD VCMPLESS VCMPLE_OQPD VCMPLE_OQPS VCMPLE_OQSD VCMPLE_OQSS VCMPLE_OSPD VCMPLE_OSPS VCMPLE_OSSD VCMPLE_OSSS VCMPLTPD VCMPLTPS VCMPLTSD VCMPLTSS VCMPLT_OQPD VCMPLT_OQPS VCMPLT_OQSD VCMPLT_OQSS VCMPLT_OSPD VCMPLT_OSPS VCMPLT_OSSD VCMPLT_OSSS VCMPNEQPD VCMPNEQPS VCMPNEQSD VCMPNEQSS VCMPNEQ_OQPD VCMPNEQ_OQPS VCMPNEQ_OQSD VCMPNEQ_OQSS VCMPNEQ_OSPD VCMPNEQ_OSPS VCMPNEQ_OSSD VCMPNEQ_OSSS VCMPNEQ_UQPD VCMPNEQ_UQPS VCMPNEQ_UQSD VCMPNEQ_UQSS VCMPNEQ_USPD VCMPNEQ_USPS VCMPNEQ_USSD VCMPNEQ_USSS VCMPNGEPD VCMPNGEPS VCMPNGESD VCMPNGESS VCMPNGE_UQPD VCMPNGE_UQPS VCMPNGE_UQSD VCMPNGE_UQSS VCMPNGE_USPD VCMPNGE_USPS VCMPNGE_USSD VCMPNGE_USSS VCMPNGTPD VCMPNGTPS VCMPNGTSD VCMPNGTSS VCMPNGT_UQPD VCMPNGT_UQPS VCMPNGT_UQSD VCMPNGT_UQSS VCMPNGT_USPD VCMPNGT_USPS VCMPNGT_USSD VCMPNGT_USSS VCMPNLEPD VCMPNLEPS VCMPNLESD VCMPNLESS VCMPNLE_UQPD VCMPNLE_UQPS VCMPNLE_UQSD VCMPNLE_UQSS VCMPNLE_USPD VCMPNLE_USPS VCMPNLE_USSD VCMPNLE_USSS VCMPNLTPD VCMPNLTPS VCMPNLTSD VCMPNLTSS VCMPNLT_UQPD VCMPNLT_UQPS VCMPNLT_UQSD VCMPNLT_UQSS VCMPNLT_USPD VCMPNLT_USPS VCMPNLT_USSD VCMPNLT_USSS VCMPORDPD VCMPORDPS VCMPORDSD VCMPORDSS VCMPORD_QPD VCMPORD_QPS VCMPORD_QSD VCMPORD_QSS VCMPORD_SPD VCMPORD_SPS VCMPORD_SSD VCMPORD_SSS VCMPPS VCMPSD VCMPPD VCMPSS VCMPTRUEPD VCMPTRUEPS VCMPTRUESD VCMPTRUESS VCMPTRUE_UQPD VCMPTRUE_UQPS VCMPTRUE_UQSD VCMPTRUE_UQSS VCMPTRUE_USPD VCMPTRUE_USPS VCMPTRUE_USSD VCMPTRUE_USSS VCMPUNORDPD VCMPUNORDPS VCMPUNORDSD VCMPUNORDSS VCMPUNORD_QPD VCMPUNORD_QPS VCMPUNORD_QSD VCMPUNORD_QSS VCMPUNORD_SPD VCMPUNORD_SPS VCMPUNORD_SSD VCMPUNORD_SSS VCOMISD VCOMISS VCOMPRESSPD VCOMPRESSPS VCVTDQ2PD VCVTDQ2PS VCVTPD2DQ VCVTPD2PS VCVTPD2QQ VCVTPD2UDQ VCVTPD2UQQ VCVTPH2PS VCVTPS2DQ VCVTPS2PD VCVTPS2PH VCVTPS2QQ VCVTPS2UDQ VCVTPS2UQQ VCVTQQ2PD VCVTQQ2PS VCVTSD2SI VCVTSD2SS VCVTSD2USI VCVTSI2SD VCVTSI2SS VCVTSS2SD VCVTSS2SI VCVTSS2USI VCVTTPD2DQ VCVTTPD2QQ VCVTTPD2UDQ VCVTTPD2UQQ VCVTTPS2DQ VCVTTPS2QQ VCVTTPS2UDQ VCVTTPS2UQQ VCVTTSD2SI VCVTTSD2USI VCVTTSS2SI VCVTTSS2USI VCVTUDQ2PD VCVTUDQ2PS VCVTUQQ2PD VCVTUQQ2PS VCVTUSI2SD VCVTUSI2SS VDBPSADBW VDIVPD VDIVPS VDIVSD VDIVSS VDPPD VDPPS VEXPANDPD VEXPANDPS VEXTRACTF128 VEXTRACTF32X4 VEXTRACTF32X8 VEXTRACTF64X2 VEXTRACTF64X4 VEXTRACTI128 VEXTRACTI32X4 VEXTRACTI32X8 VEXTRACTI64X2 VEXTRACTI64X4 VEXTRACTPS VFIXUPIMMPD VFIXUPIMMPS VFIXUPIMMSD VFIXUPIMMSS VFMADD233PS VFPCLASSPD VFPCLASSPS VFPCLASSSD VFPCLASSSS VGATHERDPD VGATHERDPS VGATHERPF0DPD VGATHERPF0DPS VGATHERPF0HINTDPD VGATHERPF0HINTDPS VGATHERPF0QPD VGATHERPF0QPS VGATHERPF1DPD VGATHERPF1DPS VGATHERPF1QPD VGATHERPF1QPS VGATHERQPD VGATHERQPS VGETEXPPD VGETEXPPS VGETEXPSD VGETEXPSS VGETMANTPD VGETMANTPS VGETMANTSD VGETMANTSS VHADDPD VHADDPS VHSUBPD VHSUBPS VINSERTF128 VINSERTF32X4 VINSERTF32X8 VINSERTF64X2 VINSERTF64X4 VINSERTI128 VINSERTI32X4 VINSERTI32X8 VINSERTI64X2 VINSERTI64X4 VINSERTPS VMAXPD VMAXPS VMAXSD VMAXSS VMINPD VMINPS VMINSD VMINSS VMOVAPD VMOVAPS VMOVD VMOVDDUP VMOVDQA VMOVDQA32 VMOVDQA64 VMOVDQU VMOVDQU16 VMOVDQU32 VMOVDQU64 VMOVDQU8 VMOVHLPS VMOVHPD VMOVHPS VMOVLHPS VMOVLPD VMOVLPS VMOVMSKPD VMOVMSKPS VMOVNRAPD VMOVNRAPS VMOVNRNGOAPD VMOVNRNGOAPS VMOVNTDQ VMOVNTDQA VMOVNTPD VMOVNTPS VMOVNTQQ VMOVQ VMOVQQA VMOVQQU VMOVSD VMOVSHDUP VMOVSLDUP VMOVSS VMOVUPD VMOVUPS VMPSADBW VMULPD VMULPS VMULSD VMULSS VPABSB VPABSD VPABSQ VPABSW VPADDB VPADDD VPADDQ VPADDSB VPADDSW VPADDUSB VPADDUSW VPADDW VPBLENDMB VPBLENDMD VPBLENDMQ VPBLENDMW VPBROADCASTB VPBROADCASTD VPBROADCASTQ VPBROADCASTW VPCOMPRESSD VPCOMPRESSQ VPEXPANDD VPEXPANDQ VPEXTRB VPEXTRD VPEXTRQ VPEXTRW VPGATHERDD VPGATHERDQ VPGATHERQD VPGATHERQQ VPINSRB VPINSRD VPINSRQ VPINSRW VPMADDWD VPMAXSB VPMAXSD VPMAXSQ VPMAXSW VPMAXUB VPMAXUD VPMAXUQ VPMAXUW VPMINSB VPMINSD VPMINSQ VPMINSW VPMINUB VPMINUD VPMINUQ VPMINUW VPMULUDQ VPSADBW VPSCATTERDD VPSCATTERDQ VPSCATTERQD VPSCATTERQQ VPSHUFB VPSHUFD VPSHUFHW VPSHUFLW VPSLLD VPSLLDQ VPSLLQ VPSLLVD VPSLLVQ VPSLLVW VPSLLW VPSRAD VPSRAQ VPSRAVD VPSRAVQ VPSRAVW VPSRAW VPSRLD VPSRLDQ VPSRLQ VPSRLVD VPSRLVQ VPSRLVW VPSRLW VPSUBB VPSUBD VPSUBQ VPSUBSB VPSUBSW VPSUBUSB VPSUBUSW VPSUBW VSCATTERDPD VSCATTERDPS VSCATTERPF0DPD VSCATTERPF0DPS VSCATTERPF0HINTDPD VSCATTERPF0HINTDPS VSCATTERPF0QPD VSCATTERPF0QPS VSCATTERPF1DPD VSCATTERPF1DPS VSCATTERPF1QPD VSCATTERPF1QPS VSCATTERQPD VSCATTERQPS VSHUFF32X4 VSHUFF64X2 VSHUFI32X4 VSHUFI64X2 VSHUFPD VSHUFPS VSUBPD VSUBPS VSUBSD VSUBSS VUCOMISD VUCOMISS

↑ IizHandlers
assemble EVEX-encodable AVX-512 machine instructions.
See also
IiHandlers, [IntelAVX512].
Available broadcasting SIMD instructions
V(P)BROADCAST8bit 16bit 32bit 64bit 128bit
int tuple1 E,VVPBROADCASTB E,VVPBROADCASTW E,VVPBROADCASTD E,VVPBROADCASTQ VVBROADCASTI128
int tuple2 EVBROADCASTI32X2 EVBROADCASTI64X2
int tuple4 E,MVBROADCASTI32X4 E,MVBROADCASTI64X4
int tuple8 EVBROADCASTI32X8
float tuple1 E,M,VVBROADCASTSS E,M,VVBROADCASTSD VVBROADCASTF128
float tuple2 EVBROADCASTF32X2 EVBROADCASTF64X2
float tuple4 E,MVBROADCASTF32X4 E,MVBROADCASTF64X4
float tuple8 EVBROADCASTF32X8
Available scalar SIMD type conversions
((e)Vex)CVT(Trunc) Scalar 2SI int32sig2USI int32uns 2SQ int64sig2USQ int64uns 2SH float162SS float32 2SD float64
SI int32sigNOP CVTSI2SS E,VVCVTSI2SS CVTSI2SD E,VVCVTSI2SD
USI int32unsNOP EVCVTUSI2SS EVCVTUSI2SD
SQ int64sigNOP
USQ int64unsNOP
SH float16 NOP
SS float32 CVTSS2SI E,VVCVTSS2SI CVTTSS2SI E,VVCVTTSS2SI EVCVTSS2USI EVCVTTSS2USI NOP CVTSS2SD E,VVCVTSS2SD
SD float64 CVTSI2SS E,VVCVTSD2SI CVTTSD2SI E,VVCVTTSD2SI EVCVTSD2USI EVCVTTSD2USI CVTSD2SS E,VVCVTSD2SS NOP
Available packed SIMD type conversions
((e)Vex)CVT(Trunc) Packed 2PI int32sig
2DQ int32sig		 2UDQ int32uns2QQ int64sig 2UQQ int64uns2PH float16 2PS float322PD float64
PI int32sig
DQ int32sig		NOP CVTPI2PS CVTDQ2PS E,VVCVTDQ2PS CVTPI2PD CVTDQ2PD E,M,VVCVTDQ2PD
UDQ int32unsNOP EVCVTUDQ2PS E,MVCVTUDQ2PD
QQ int64sigNOP EVCVTQQ2PS EVCVTQQ2PD
UQQ int64uns NOP EVCVTUQQ2PS EVCVTUQQ2PD
PH float16 NOP E,VVCVTPH2PS
PS float32 CVTPS2PI CVTPS2DQ E,VVCVTPS2DQ CVTTPS2PI CVTTPS2DQ E,VVCVTTPS2DQ EVCVTPS2UDQ EVCVTTPS2UDQ EVCVTPS2QQ EVCVTTPS2QQ EVCVTPS2UQQ EVCVTTPS2UQQ E,VVCVTPS2PH NOPCVTPS2PD E,M,VVCVTPS2PD
PD float64 CVTPD2PI CVTPD2DQ E,VVCVTPD2DQ CVTTPD2PI CVTTPD2DQ E,VVCVTTPD2DQ EVCVTPD2UDQ EVCVTTPD2UDQ EVCVTPD2QQ EVCVTTPD2QQ EVCVTPD2UQQ EVCVTTPD2UQQ CVTPD2PS E,M,VVCVTPD2PS NOP

iiz PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32,MAXPASSES=48
 INCLUDEHEAD "euroasm.htm" ; Interface (structures, symbols and macros) of other modules.

iiz HEAD ; Start of module interface.
↑ %IizList
enumerates machine instructions of this family which €ASM can assemble.
Each instruction declared in %IizList requires the corresponding handler in this file.
See also
DictLookupIi
%IizList %SET \
VADDPD, \
VADDPS, \
VADDSS, \
VADDSD, \
VMULSD, \
VMULSS, \
VMULPS, \
VMULPD, \
VSUBPS, \
VSUBPD, \
VSUBSS, \
VSUBSD, \
VDIVPS, \
VDIVPD, \
VDIVSS, \
VDIVSD, \
VMINPS, \
VMINPD, \
VMAXPD, \
VMINSS, \
VMAXSS, \
VMINSD, \
VMAXSD, \
VMAXPS, \
VCVTPS2PD, \
VCVTPD2PS, \
VCVTSS2SD, \
VCVTSD2SS, \
VCVTDQ2PS, \
VCVTPS2DQ, \
VCVTTPS2DQ, \
VCVTQQ2PS, \
VCVTSI2SS, \
VCVTSI2SD, \
VCVTSS2SI, \
VCVTSD2SI, \
VCVTTSS2SI, \
VCVTTSD2SI, \
VCVTSS2USI, \
VCVTSD2USI, \
VCVTTSS2USI, \
VCVTTSD2USI, \
VCVTUSI2SS, \
VCVTUSI2SD, \
VCVTUDQ2PS, \
VCVTUDQ2PD, \
VCVTTPS2UDQ, \
VCVTTPD2UDQ, \
VCVTTPS2UQQ, \
VCVTTPD2UQQ, \
VCVTPS2UDQ, \
VCVTPD2UDQ, \
VCVTPS2UQQ, \
VCVTTPS2QQ, \
VCVTPS2QQ, \
VCVTTPD2QQ, \
VCVTPD2UQQ, \
VCVTPD2QQ, \
VCVTTPD2DQ, \
VCVTPD2DQ, \
VCVTDQ2PD, \
VCVTQQ2PD, \
VCVTUQQ2PS, \
VCVTUQQ2PD, \
VCVTPH2PS, \
VCVTPS2PH, \
VBROADCASTSS, \
VBROADCASTSD, \
VBROADCASTF128, \
VBROADCASTF32X2, \
VBROADCASTF32X4, \
VBROADCASTF32X8, \
VBROADCASTF64X2, \
VBROADCASTF64X4, \
VBROADCASTI32X4, \
VBROADCASTI64X4, \
VBROADCASTI32X2, \
VBROADCASTI128, \
VBROADCASTI64X2, \
VBROADCASTI32X8, \
VPBROADCASTB, \
VPBROADCASTW, \
VPBROADCASTD, \
VPBROADCASTQ, \
VALIGND, \
VALIGNQ, \
VPBLENDMB, \
VPBLENDMW, \
VPBLENDMD, \
VPBLENDMQ, \
VBLENDMPS, \
VBLENDMPD, \
VCMPSS, \
VCMPSD, \
VCMPPS, \
VCMPPD, \
VCMPEQSS, \
VCMPLTSS, \
VCMPLESS, \
VCMPUNORDSS, \
VCMPNEQSS, \
VCMPNLTSS, \
VCMPNLESS, \
VCMPORDSS, \
VCMPNGESS, \
VCMPNGTSS, \
VCMPFALSESS, \
VCMPGESS, \
VCMPGTSS, \
VCMPTRUESS, \
VCMPEQ_OQSS, \
VCMPLT_OSSS, \
VCMPLE_OSSS, \
VCMPUNORD_QSS, \
VCMPNEQ_UQSS, \
VCMPNLT_USSS, \
VCMPNLE_USSS, \
VCMPORD_QSS, \
VCMPEQ_UQSS, \
VCMPNGE_USSS, \
VCMPNGT_USSS, \
VCMPFALSE_OQSS, \
VCMPNEQ_OQSS, \
VCMPGE_OSSS, \
VCMPGT_OSSS, \
VCMPTRUE_UQSS, \
VCMPEQ_OSSS, \
VCMPLT_OQSS, \
VCMPLE_OQSS, \
VCMPUNORD_SSS, \
VCMPNEQ_USSS, \
VCMPNLT_UQSS, \
VCMPNLE_UQSS, \
VCMPORD_SSS, \
VCMPEQ_USSS, \
VCMPNGE_UQSS, \
VCMPNGT_UQSS, \
VCMPFALSE_OSSS, \
VCMPNEQ_OSSS, \
VCMPGE_OQSS, \
VCMPGT_OQSS, \
VCMPTRUE_USSS, \
VCMPEQSD, \
VCMPLTSD, \
VCMPLESD, \
VCMPUNORDSD, \
VCMPNEQSD, \
VCMPNLTSD, \
VCMPNLESD, \
VCMPORDSD, \
VCMPNGESD, \
VCMPNGTSD, \
VCMPFALSESD, \
VCMPGESD, \
VCMPGTSD, \
VCMPTRUESD, \
VCMPEQ_OQSD, \
VCMPLT_OSSD, \
VCMPLE_OSSD, \
VCMPUNORD_QSD, \
VCMPNEQ_UQSD, \
VCMPNLT_USSD, \
VCMPNLE_USSD, \
VCMPORD_QSD, \
VCMPEQ_UQSD, \
VCMPNGE_USSD, \
VCMPNGT_USSD, \
VCMPFALSE_OQSD, \
VCMPNEQ_OQSD, \
VCMPGE_OSSD, \
VCMPGT_OSSD, \
VCMPTRUE_UQSD, \
VCMPEQ_OSSD, \
VCMPLT_OQSD, \
VCMPLE_OQSD, \
VCMPUNORD_SSD, \
VCMPNEQ_USSD, \
VCMPNLT_UQSD, \
VCMPNLE_UQSD, \
VCMPORD_SSD, \
VCMPEQ_USSD, \
VCMPNGE_UQSD, \
VCMPNGT_UQSD, \
VCMPFALSE_OSSD, \
VCMPNEQ_OSSD, \
VCMPGE_OQSD, \
VCMPGT_OQSD, \
VCMPTRUE_USSD, \
VCMPEQPS, \
VCMPLTPS, \
VCMPLEPS, \
VCMPUNORDPS, \
VCMPNEQPS, \
VCMPNLTPS, \
VCMPNLEPS, \
VCMPORDPS, \
VCMPNGEPS, \
VCMPNGTPS, \
VCMPFALSEPS, \
VCMPGEPS, \
VCMPGTPS, \
VCMPTRUEPS, \
VCMPEQ_OQPS, \
VCMPLT_OSPS, \
VCMPLE_OSPS, \
VCMPUNORD_QPS, \
VCMPNEQ_UQPS, \
VCMPNLT_USPS, \
VCMPNLE_USPS, \
VCMPORD_QPS, \
VCMPEQ_UQPS, \
VCMPNGE_USPS, \
VCMPNGT_USPS, \
VCMPFALSE_OQPS, \
VCMPNEQ_OQPS, \
VCMPGE_OSPS, \
VCMPGT_OSPS, \
VCMPTRUE_UQPS, \
VCMPEQ_OSPS, \
VCMPLT_OQPS, \
VCMPLE_OQPS, \
VCMPUNORD_SPS, \
VCMPNEQ_USPS, \
VCMPNLT_UQPS, \
VCMPNLE_UQPS, \
VCMPORD_SPS, \
VCMPEQ_USPS, \
VCMPNGE_UQPS, \
VCMPNGT_UQPS, \
VCMPFALSE_OSPS, \
VCMPNEQ_OSPS, \
VCMPGE_OQPS, \
VCMPGT_OQPS, \
VCMPTRUE_USPS, \
VCMPEQPD, \
VCMPLTPD, \
VCMPLEPD, \
VCMPUNORDPD, \
VCMPNEQPD, \
VCMPNLTPD, \
VCMPNLEPD, \
VCMPORDPD, \
VCMPNGEPD, \
VCMPNGTPD, \
VCMPFALSEPD, \
VCMPGEPD, \
VCMPGTPD, \
VCMPTRUEPD, \
VCMPEQ_OQPD, \
VCMPLT_OSPD, \
VCMPLE_OSPD, \
VCMPUNORD_QPD, \
VCMPNEQ_UQPD, \
VCMPNLT_USPD, \
VCMPNLE_USPD, \
VCMPORD_QPD, \
VCMPEQ_UQPD, \
VCMPNGE_USPD, \
VCMPNGT_USPD, \
VCMPFALSE_OQPD, \
VCMPNEQ_OQPD, \
VCMPGE_OSPD, \
VCMPGT_OSPD, \
VCMPTRUE_UQPD, \
VCMPEQ_OSPD, \
VCMPLT_OQPD, \
VCMPLE_OQPD, \
VCMPUNORD_SPD, \
VCMPNEQ_USPD, \
VCMPNLT_UQPD, \
VCMPNLE_UQPD, \
VCMPORD_SPD, \
VCMPEQ_USPD, \
VCMPNGE_UQPD, \
VCMPNGT_UQPD, \
VCMPFALSE_OSPD, \
VCMPNEQ_OSPD, \
VCMPGE_OQPD, \
VCMPGT_OQPD, \
VCMPTRUE_USPD, \
VUCOMISS, \
VUCOMISD, \
VCOMISS, \
VCOMISD, \
VCOMPRESSPS, \
VCOMPRESSPD, \
VPCOMPRESSD, \
VPCOMPRESSQ, \
VMPSADBW, \
VDBPSADBW, \
VDPPS, \
VDPPD, \
VEXPANDPS, \
VEXPANDPD, \
VPEXPANDD, \
VPEXPANDQ, \
VEXTRACTF32X4, \
VEXTRACTF32X8, \
VEXTRACTF64X2, \
VEXTRACTF64X4, \
VEXTRACTF128, \
VEXTRACTPS, \
VEXTRACTI32X4, \
VEXTRACTI32X8, \
VEXTRACTI64X2, \
VEXTRACTI64X4, \
VEXTRACTI128, \
VPEXTRB, \
VPEXTRW, \
VPEXTRD, \
VPEXTRQ, \
VINSERTF32X4, \
VINSERTF32X8, \
VINSERTF64X2, \
VINSERTF64X4, \
VINSERTF128, \
VINSERTI32X4, \
VINSERTI32X8, \
VINSERTI64X2, \
VINSERTI64X4, \
VINSERTI128, \
VINSERTPS, \
VPINSRB, \
VPINSRW, \
VPINSRD, \
VPINSRQ, \
VFIXUPIMMSS, \
VFIXUPIMMSD, \
VFIXUPIMMPS, \
VFIXUPIMMPD, \
VFPCLASSSS, \
VFPCLASSSD, \
VFPCLASSPS, \
VFPCLASSPD, \
VPGATHERDD, \
VPGATHERQD, \
VPGATHERQQ, \
VPGATHERDQ, \
VGATHERDPS, \
VGATHERDPD, \
VGATHERQPS, \
VGATHERQPD, \
VGATHERPF0DPS, \
VGATHERPF0HINTDPS, \
VGATHERPF0QPS, \
VGATHERPF0DPD, \
VGATHERPF0HINTDPD, \
VGATHERPF0QPD, \
VGATHERPF1DPS, \
VGATHERPF1QPS, \
VGATHERPF1DPD, \
VGATHERPF1QPD, \
VPSCATTERDD, \
VPSCATTERDQ, \
VPSCATTERQD, \
VPSCATTERQQ, \
VSCATTERDPS, \
VSCATTERDPD, \
VSCATTERQPS, \
VSCATTERQPD, \
VSCATTERPF0DPS, \
VSCATTERPF0HINTDPS, \
VSCATTERPF0QPS, \
VSCATTERPF0DPD, \
VSCATTERPF0HINTDPD, \
VSCATTERPF0QPD, \
VSCATTERPF1DPS, \
VSCATTERPF1QPS, \
VSCATTERPF1DPD, \
VSCATTERPF1QPD, \
VGETEXPSS, \
VGETEXPSD, \
VGETEXPPS, \
VGETEXPPD, \
VGETMANTSS, \
VGETMANTSD, \
VGETMANTPS, \
VGETMANTPD, \
VMOVAPS, \
VMOVAPD, \
VMOVD, \
VMOVQ, \
VMOVSS, \
VMOVSD, \
VMOVUPS, \
VMOVUPD, \
VMOVLPS, \
VMOVHPS, \
VMOVLPD, \
VMOVHPD, \
VMOVLHPS, \
VMOVHLPS, \
VMOVSLDUP, \
VMOVSHDUP, \
VMOVDQA, \
VMOVQQA, \
VMOVDQA32, \
VMOVDQA64, \
VMOVDQU, \
VMOVQQU, \
VMOVDQU8, \
VMOVDQU16, \
VMOVDQU32, \
VMOVDQU64, \
VMOVMSKPS, \
VMOVMSKPD, \
VMOVNTPS, \
VMOVNTPD, \
VMOVNTDQ, \
VMOVNTQQ, \
VMOVNTDQA, \
VMOVDDUP, \
VADDSUBPS, \
VADDSUBPD, \
VPMINUB, \
VPMINUW, \
VPMINUD, \
VPMINUQ, \
VPMINSB, \
VPMINSW, \
VPMINSD, \
VPMINSQ, \
VPMAXSB, \
VPMAXSW, \
VPMAXSD, \
VPMAXSQ, \
VPMAXUB, \
VPMAXUW, \
VPMAXUD, \
VPMAXUQ, \
VPADDB, \
VPADDW, \
VPADDD, \
VPADDQ, \
VPADDSB, \
VPADDSW, \
VPSUBB, \
VPSUBW, \
VPSUBD, \
VPSUBQ, \
VPSUBSB, \
VPSUBSW, \
VPADDUSB, \
VPADDUSW, \
VPSUBUSB, \
VPSUBUSW, \
VHADDPS, \
VHADDPD, \
VHSUBPS, \
VHSUBPD, \
VPSRLW, \
VPSRLD, \
VPSRLQ, \
VPSRLDQ, \
VPSRAW, \
VPSRAD, \
VPSRAQ, \
VPSLLW, \
VPSLLD, \
VPSLLQ, \
VPSLLDQ, \
VPSRLVW, \
VPSRLVD, \
VPSRLVQ, \
VPSRAVW, \
VPSRAVD, \
VPSRAVQ, \
VPSLLVW, \
VPSLLVD, \
VPSLLVQ, \
VPABSB, \
VPABSW, \
VPABSD, \
VPABSQ, \
VPMULUDQ, \
VPMADDWD, \
VPSADBW, \
VSHUFPS, \
VSHUFPD, \
VSHUFF32X4, \
VSHUFF64X2, \
VSHUFI32X4, \
VSHUFI64X2, \
VPSHUFB, \
VPSHUFLW, \
VPSHUFHW, \
VPSHUFD, \
VFMADD233PS, \
VMOVNRAPS, \
VMOVNRAPD, \
VMOVNRNGOAPS, \
VMOVNRNGOAPD, \

;

  ENDHEAD iiz ; End of module interface.
↑ IizGroupVADDPS
IizGroupVADDPS is a common handler for VEX/MVEX/EVEX encodable instructions in following formats:
Intel reference
xmm1,xmm2,xmm3/m128 VEX.NDS.128.0F.WIG opcode /r
ymm1, ymm2,ymm3/m256 VEX.NDS.256.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2,xmm3/m128/m32bcst EVEX.NDS.128.0F.W0 opcode /r
ymm1 {k1}{z}, ymm2,ymm3/m256/m32bcst EVEX.NDS.256.0F.W0 opcode /r
zmm1 {k1}{z}, zmm2,zmm3/m512/m32bcst {er} EVEX.NDS.512.0F.W0 opcode /r
zmm1 {k1}, zmm2,zmm3/m512/m32bcst {er} MVEX.NDS.512.0F.W0 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5212 
IizGroupVADDPS PROC
    IiAllowModifier MASK,EH
    IiAllowBroadcasting DWORD
    IiEmitOpcode EAX    
    IiDisp8EVEX FV32
    IiAllowRounding
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
    IiEmitPrefix VEX.NDS.128.0F.WIG, EVEX.NDS.128.0F.W0
    RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
    IiEmitPrefix VEX.NDS.256.0F.WIG, EVEX.NDS.256.0F.W0
    RET
.zmm.zmm.mem:
    IiDisp8MVEX Us32
.zmm.zmm.zmm:
    IiEmitPrefix EVEX.NDS.512.0F.W0
    CMP AL,0x5C ; VDIVPS does not have MVEX form.
    JA .90: 
    IiEmitPrefix MVEX.NDS.512.0F.W0
.90:RET
    ENDP IizGroupVADDPS
↑ VADDPS
Add Packed Single-FP Values
Category
sse1,simdfp,arith
Operands
Vps,Wps
Opcode
0x0F58 /r
CPU
P3+
Tested by
t5212 
IizVADDPS:: PROC
    MOV AL,0x58
    JMP IizGroupVADDPS
  ENDP IizVADDPS::
↑ VMULPS
Multiply Packed Single-FP Values
Category
sse1,simdfp,arith
Operands
Vps,Wps
Opcode
0x0F59 /r
CPU
P3+
Tested by
t5212 
IizVMULPS:: PROC
    MOV AL,0x59
    JMP IizGroupVADDPS
 ENDP IizVMULPS::
↑ VSUBPS
Subtract Packed Single-FP Values
Category
sse1,simdfp,arith
Operands
Vps,Wps
Opcode
0x0F5C /r
CPU
P3+
Tested by
t5212 
IizVSUBPS:: PROC
    MOV AL,0x5C
    JMP IizGroupVADDPS
 ENDP IizVSUBPS::
↑ VDIVPS
Divide Packed Single-FP Values
Category
sse1,simdfp,arith
Operands
Vps,Wps
Opcode
0x0F5E /r
CPU
P3+
Tested by
t5212 
IizVDIVPS:: PROC
    MOV AL,0x5E
    JMP IizGroupVADDPS
 ENDP IizVDIVPS::
↑ IizGroupVADDPD
IizGroupVADDPD is a common handler for VEX/MVEX/EVEX encodable instructions in following formats:
Intel reference
xmm1,xmm2,xmm3/m128 VEX.NDS.128.66.0F.WIG opcode /r
ymm1, ymm2,ymm3/m256 VEX.NDS.256.66.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2,xmm3/m128/m32bcst EVEX.NDS.128.66.0F.W1 opcode /r
ymm1 {k1}{z}, ymm2,ymm3/m256/m32bcst EVEX.NDS.256.66.0F.W1 opcode /r
zmm1 {k1}{z}, zmm2,zmm3/m512/m32bcst {er} EVEX.NDS.512.66.0F.W1 opcode /r
zmm1 {k1}, zmm2,zmm3/m512/m32bcst {er} MVEX.NDS.512.66.0F.W1 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5212 
IizGroupVADDPD:: PROC
    IiAllowModifier MASK,EH
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode EAX
    IiEncoding DATA=QWORD
    IiDisp8EVEX FV64
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W1
    RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W1
    RET
.zmm.zmm.mem:    
    IiDisp8MVEX Ub64
.zmm.zmm.zmm:
    IiEmitPrefix EVEX.NDS.512.66.0F.W1
    CMP AL,0x5C ; VDIVPD does not have MVEX form.
    JA .90:
    IiEmitPrefix MVEX.NDS.512.66.0F.W1
.90:RET
   ENDPROC IizGroupVADDPD
↑ VADDPD
Add Packed Double-FP Values
Category
sse2,simdfp,arith
Operands
Vpd,Wpd
Opcode
0x660F58 /r
CPU
P4+
Tested by
t5212 
IizVADDPD:: PROC
    MOV AL,0x58
    JMP IizGroupVADDPD
  ENDP IizVADDPD::
↑ VMULPD
Multiply Packed Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vpd,Wpd
Opcode
0x660F59 /r
CPU
P4+
Tested by
t5212 
IizVMULPD:: PROC
    MOV AL,0x59
    JMP IizGroupVADDPD
 ENDP IizVMULPD::
↑ VSUBPD
Subtract Packed Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vpd,Wpd
Opcode
0x660F5C /r
CPU
P4+
Tested by
t5212 
IizVSUBPD:: PROC
    MOV AL,0x5C
    JMP IizGroupVADDPD
 ENDP IizVSUBPD::
↑ VDIVPD
Divide Packed Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vpd,Wpd
Opcode
0x660F5E /r
CPU
P4+
Tested by
t5212 
IizVDIVPD:: PROC
    MOV AL,0x5E
    JMP IizGroupVADDPD
 ENDP IizVDIVPD::
↑ IizGroupVADDSS
IizGroupVADDSS is a common handler for VEX/MVEX/EVEX encodable instructions in following formats:
Intel reference
xmm1,xmm2,xmm3/m32 VEX.NDS.128.F3.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2,xmm3/m32{er} EVEX.NDS.LIG.F3.0F.W0 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5210 
IizGroupVADDSS:: PROC
    IiAllowModifier MASK
    IiAllowRounding Register=xmm
    IiEmitOpcode EAX
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiEmitPrefix VEX.NDS.128.F3.0F.WIG, EVEX.NDS.LIG.F3.0F.W0
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
   ENDPROC IizGroupVADDSS
↑ VADDSS
Add Scalar Single-FP Values
Category
sse1,simdfp,arith
Operands
Vss,Wss
Opcode
0xF30F58 /r
CPU
P3+
Tested by
t5210 
IizVADDSS:: PROC
    MOV AL,0x58
    JMP IizGroupVADDSS
 ENDP IizVADDSS::
↑ VMULSS
Multiply Scalar Single-FP Value
Category
sse1,simdfp,arith
Operands
Vss,Wss
Opcode
0xF30F59 /r
CPU
P3+
Tested by
t5210 
IizVMULSS:: PROC
    MOV AL,0x59
    JMP IizGroupVADDSS
 ENDP IizVMULSS::
↑ VSUBSS
Subtract Scalar Single-FP Values
Category
sse1,simdfp,arith
Operands
Vss,Wss
Opcode
0xF30F5C /r
CPU
P3+
Tested by
t5210 
IizVSUBSS:: PROC
    MOV AL,0x5C
    JMP IizGroupVADDSS
 ENDP IizVSUBSS::
↑ VDIVSS
Divide Scalar Single-FP Values
Category
sse1,simdfp,arith
Operands
Vss,Wss
Opcode
0xF30F5E /r
CPU
P3+
Tested by
t5210 
IizVDIVSS:: PROC
    MOV AL,0x5E
    JMP IizGroupVADDSS
 ENDP IizVDIVSS::
↑ IizGroupVADDSD
IizGroupVADDSD is a common handler for VEX/MVEX/EVEX encodable instructions in following formats:
Intel reference
xmm1,xmm2,xmm3/m64 VEX.NDS.128.F2.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2,xmm3/m64{er} EVEX.NDS.LIG.F2.0F.W1 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5210 
IizGroupVADDSD:: PROC
    IiAllowModifier MASK
    IiAllowRounding Register=xmm
    IiEmitOpcode EAX
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiEmitPrefix VEX.NDS.128.F2.0F.WIG, EVEX.NDS.LIG.F2.0F.W1
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
   ENDPROC IizGroupVADDSD
↑ VADDSD
Add Scalar Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vsd,Wsd
Opcode
0xF20F58 /r
CPU
P4+
Tested by
t5210 
IizVADDSD:: PROC
    MOV AL,0x58
    JMP IizGroupVADDSD
 ENDP IizVADDSD::
↑ VMULSD
Multiply Scalar Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vsd,Wsd
Opcode
0xF20F59 /r
CPU
P4+
Tested by
t5210 
IizVMULSD:: PROC
    MOV AL,0x59
    JMP IizGroupVADDSD
 ENDP IizVMULSD::
↑ VSUBSD
Subtract Scalar Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vsd,Wsd
Opcode
0xF20F5C /r
CPU
P4+
Tested by
t5210 
IizVSUBSD:: PROC
    MOV AL,0x5C
    JMP IizGroupVADDSD
 ENDP IizVSUBSD::
↑ VDIVSD
Divide Scalar Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vsd,Wsd
Opcode
0xF20F5E /r
CPU
P4+
Tested by
t5210 
IizVDIVSD:: PROC
    MOV AL,0x5E
    JMP IizGroupVADDSD
 ENDP IizVDIVSD::
↑ IizGroupVMINPS
IizGroupVMINPS is a common handler for instructions in following formats:
Intel reference
xmm1,xmm2, xmm3/m128 VEX.NDS.128.0F.WIG opcode /r
ymm1, ymm2, ymm3/m256 VEX.NDS.256.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.0F.W0 opcode /r
ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.0F.W0 opcode /r
zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst {sae} EVEX.NDS.512.0F.W0 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5216 
IizGroupVMINPS:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowSuppressing 
    IiEmitOpcode EAX
    IiDisp8EVEX FV32
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
    IiEmitPrefix VEX.NDS.128.0F.WIG, EVEX.NDS.128.0F.W0
    RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
    IiEmitPrefix VEX.NDS.256.0F.WIG, EVEX.NDS.256.0F.W0
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:    
    IiEmitPrefix EVEX.NDS.512.0F.W0
    RET
   ENDPROC IizGroupVMINPS
↑ VMINPS
Return Minimum Packed Single-FP Values
Category
sse1,simdfp,arith
Operands
Vps,Wps
Opcode
0x0F5D /r
CPU
P3+
Tested by
t5216 
IizVMINPS:: PROC
    MOV AL,0x5D
    JMP IizGroupVMINPS
 ENDP IizVMINPS::
↑ VMAXPS
Return Maximum Packed Single-FP Values
Category
sse1,simdfp,arith
Operands
Vps,Wps
Opcode
0x0F5F /r
CPU
P3+
Tested by
t5216 
IizVMAXPS:: PROC
     MOV AL,0x5F
     JMP IizGroupVMINPS
 ENDP IizVMAXPS::
↑ IizGroupVMINPD
IizGroupVMINPD is a common handler for instructions in following formats:
Intel reference
xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG opcode /r
ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F.W1 opcode /r
ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F.W0 opcode /r
zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst {sae} EVEX.NDS.512.66.0F.W0 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5216 
IizGroupVMINPD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowSuppressing
    IiEmitOpcode EAX
    IiDisp8EVEX FV64
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W1
    RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:    
    IiEmitPrefix EVEX.NDS.512.66.0F.W1
    RET
    ENDPROC IizGroupVMINPD
↑ VMINPD
Return Minimum Packed Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vpd,Wpd
Opcode
0x660F5D /r
CPU
P4+
Tested by
t5216 
IizVMINPD:: PROC
    MOV AL,0x5D
    JMP IizGroupVMINPD
 ENDP IizVMINPD::
↑ VMAXPD
Return Maximum Packed Double-FP Values
Category
sse2,pcksclr,arith
Operands
Vpd,Wpd
Opcode
0x660F5F /r
CPU
P4+
Tested by
t5216 
IizVMAXPD:: PROC
    MOV AL,0x5F
    JMP IizGroupVMINPD
 ENDP IizVMAXPD::
↑ IizGroupVMINSS
IizGroupVMINSS is a common handler for VEX/MVEX/EVEX encodable instructions in following formats:
Intel reference
xmm1,xmm2,xmm3/m32 VEX.NDS.128.F3.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2,xmm3/m32{sae} EVEX.NDS.LIG.F3.0F.W0 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5214 
IizGroupVMINSS:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Register=xmm
    IiEncoding DATA=DWORD
    IiEmitOpcode EAX
    IiDisp8EVEX T1S32
    IiOpEn RVM
    IiModRM /r
    IiEmitPrefix VEX.NDS.128.F3.0F.WIG, EVEX.NDS.LIG.F3.0F.W0    
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
    ENDPROC IizGroupVMINSS
↑ VMINSS
Return Minimum Scalar Single-FP Value
Category
sse1,simdfp,arith
Operands
Vss,Wss
Opcode
0xF30F5D /r
CPU
P3+
Tested by
t5214 
IizVMINSS:: PROC
    MOV AL,0x5D
    JMP IizGroupVMINSS
 ENDP IizVMINSS::
↑ VMAXSS
Return Maximum Scalar Single-FP Value
Category
sse1,simdfp,arith
Operands
Vss,Wss
Opcode
0xF30F5F /r
CPU
P3+
Tested by
t5214 
IizVMAXSS:: PROC
    MOV AL,0x5F
    JMP IizGroupVMINSS
 ENDP IizVMAXSS::
↑ IizGroupVMINSD
IizGroupVMINSD is a common handler for VEX/MVEX/EVEX encodable instructions in following formats:
Intel reference
xmm1, xmm2, xmm3/m64 VEX.NDS.128.F2.0F.WIG opcode /r
xmm1 {k1}{z}, xmm2, xmm3/m64{sae} EVEX.NDS.LIG.F2.0F.W1 opcode /r
Input
AL is opcode byte.
EDX has operand types as set by IiAssemble.
EDI is pointer to II structure with parsed operands.
Called by
 
Tested by
t5214 
IizGroupVMINSD:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Register=xmm
    IiEmitOpcode EAX
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiOpEn RVM
    IiModRM /r
    IiEmitPrefix VEX.NDS.128.F2.0F.WIG, EVEX.NDS.LIG.F2.0F.W1
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
    ENDPROC IizGroupVMINSD
↑ VMINSD
Return Minimum Scalar Double-FP Value
Category
sse2,pcksclr,arith
Operands
Vsd,Wsd
Opcode
0xF20F5D /r
CPU
P4+
Tested by
t5214 
IizVMINSD:: PROC
    MOV AL,0x5D
    JMP IizGroupVMINSD
 ENDP IizVMINSD::
↑ VMAXSD
Return Maximum Scalar Double-FP Value
Category
sse2,pcksclr,arith
Operands
Vsd,Wsd
Opcode
0xF20F5F /r
CPU
P4+
Tested by
t5214 
IizVMAXSD:: PROC
    MOV AL,0x5F
    JMP IizGroupVMINSD
 ENDP IizVMAXSD::
↑ VCVTPS2PD
Convert Packed Single-FP Values to Double-FP Values
Intel reference
VCVTPS2PD xmm1, xmm2/m64 VEX.128.0F.WIG 5A /r
VCVTPS2PD ymm1, xmm2/m128 VEX.256.0F.WIG 5A /r
VCVTPS2PD xmm1 {k1}{z}, xmm2/m64/m32bcst EVEX.128.0F.W0 5A /r
VCVTPS2PD ymm1 {k1}{z}, xmm2/m128/m32bcst EVEX.256.0F.W0 5A /r
VCVTPS2PD zmm1 {k1}{z}, ymm2/m256/m32bcst{sae} EVEX.512.0F.W0 5A /r
VCVTPS2PD zmm1 {k1}, zmm2/mem MVEX.512.0F.W0 5A /r
Category
sse2,pcksclr,conver
Operands
Vpd,Wps
Opcode
0x0F5A /r
CPU
P4+
Tested by
t5230 
IizVCVTPS2PD:: PROC
   IiEmitOpcode 0x5A
   IiAllowModifier MASK
   IiAllowBroadcasting DWORD
   IiAllowSuppressing Register=ymm
   IiDisp8EVEX HV32
   IiOpEn RM
   IiModRM /r
   IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem, zmm.zmm
.xmm.mem:
.xmm.xmm:
   IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
   RET
.ymm.mem:
.ymm.xmm:
   IiEmitPrefix VEX.256.0F.WIG, EVEX.256.0F.W0
   RET
.zmm.ymm:
   IiEmitPrefix EVEX.512.0F.W0
   RET
.zmm.mem:
   JNSt [EDI+II.MfxExplicit],iiMfxPREFIX_MVEX, .zmm.ymm:
   IiDisp8MVEX Sb32
.zmm.zmm:
   IiEmitPrefix MVEX.512.0F.W0
   RET
  ENDP IizVCVTPS2PD::
↑ VCVTPD2PS
Convert Packed Double-FP Values to Single-FP Values
Intel reference
VCVTPD2PS xmm1, xmm2/m128 VEX.128.66.0F.WIG 5A /r
VCVTPD2PS xmm1, ymm2/m256 VEX.256.66.0F.WIG 5A /r
VCVTPD2PS xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F.W1 5A /r
VCVTPD2PS xmm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F.W1 5A /r
VCVTPD2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.66.0F.W1 5A /r
VCVTPD2PS zmm1 {k1}, zmm2/m512/mem MVEX.512.66.0F.W1 5A /r
Category
sse2,pcksclr,conver
Operands
Vps,Wpd
Opcode
0x660F5A /r
CPU
P4+
Tested by
t5228 
IizVCVTPD2PS:: PROC
    IiAllowModifier DATA,MASK
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode 0x5A
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
    IiDispatchDataSize OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
    IiAbort '6793'  ; Please specify memory operand size with DATA=OWORD or DATA=YWORD.
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
    IiEncoding DATA=QWORD
    RET
.xmm.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W1
    IiEncoding DATA=OWORD
    RET
.ymm.zmm:
.ymm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1
    IiEncoding DATA=YWORD
    RET
.zmm.mem:
    IiDisp8MVEX Ub64
.zmm.zmm:
    IiEmitPrefix MVEX.512.66.0F.W1
    IiEncoding DATA=YWORD
    RET
  ENDP IizVCVTPD2PS::
↑ VCVTSS2SD
Convert Scalar Single-FP Value to Scalar Double-FP Value
Intel reference
VCVTSS2SD xmm1, xmm2, xmm3/m32 VEX.NDS.128.F3.0F.WIG 5A /r
VCVTSS2SD xmm1 {k1}{z}, xmm2, xmm3/m32{sae} EVEX.NDS.LIG.F3.0F.W0 5A /r
Category
sse2,pcksclr,conver
Operands
Vsd,Wss
Opcode
0xF30F5A /r
CPU
P4+
Tested by
t5222 
IizVCVTSS2SD:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Register=xmm
    IiEmitOpcode 0x5A
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiEmitPrefix VEX.NDS.128.F3.0F.WIG, EVEX.NDS.LIG.F3.0F.W0
    IiOpEn RVM
    IiModRM /r    
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
  ENDP IizVCVTSS2SD::
↑ VCVTSD2SS
Convert Scalar Double-FP Value to Scalar Single-FP Value
Intel reference
VCVTSD2SS xmm1,xmm2, xmm3/m64 VEX.NDS.128.F2.0F.WIG 5A /r
VCVTSD2SS xmm1 {k1}{z}, xmm2, xmm3/m64{er} EVEX.NDS.LIG.F2.0F.W1 5A /r
Category
sse2,pcksclr,conver
Operands
Vss,Wsd
Opcode
0xF20F5A /r
CPU
P4+
Tested by
t5222 
IizVCVTSD2SS:: PROC
    IiAllowModifier MASK
    IiAllowRounding Register=xmm
    IiEmitOpcode 0x5A
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiEmitPrefix VEX.NDS.128.F2.0F.WIG, EVEX.NDS.LIG.F2.0F.W1
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
  ENDP IizVCVTSD2SS::
↑ VCVTDQ2PS
Convert Packed DW Integers to Single-FP Values
Intel reference
VCVTDQ2PS xmm1, xmm2/m128 VEX.128.0F.WIG 5B /r
VCVTDQ2PS ymm1, ymm2/m256 VEX.256.0F.WIG 5B /r
VCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.0F.W0 5B /r
VCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.0F.W0 5B /r
VCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er} EVEX.512.0F.W0 5B /r
Category
sse2,pcksp
Operands
Vps,Wdq
Opcode
0x0F5B /r
CPU
P4+
Tested by
t5228 
IizVCVTDQ2PS:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowRounding
    IiEmitOpcode 0x5B
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
    RET
.ymm.mem:
.ymm.ymm:
    IiEmitPrefix VEX.256.0F.WIG, EVEX.256.0F.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.0F.W0
    RET
  ENDP IizVCVTDQ2PS::
↑ VCVTPS2DQ
Convert Packed Single-FP Values to DWORD Integers
Intel reference
VCVTPS2DQ xmm1, xmm2/m128 VEX.128.66.0F.WIG 5B /r
VCVTPS2DQ ymm1, ymm2/m256 VEX.256.66.0F.WIG 5B /r
VCVTPS2DQ xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.66.0F.W0 5B /r
VCVTPS2DQ ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.66.0F.W0 5B /r
VCVTPS2DQ zmm1 {k1}{z}, zmm2/m512/m32bcst{er} EVEX.512.66.0F.W0 5B /r
Category
sse2,pcksp
Operands
Vdq,Wps
Opcode
0x660F5B /r
CPU
P4+
Tested by
t5224 
IizVCVTPS2DQ:: PROC
    IiAllowModifier DATA,MASK
    IiAllowBroadcasting DWORD
    IiAllowRounding
    IiEmitOpcode 0x5B
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W0
    RET
.ymm.mem:
.ymm.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W0
    RET
  ENDP IizVCVTPS2DQ::
↑ VCVTTPS2DQ
Convert with Trunc. Packed Single-FP Values to DW Integers
Intel reference
VCVTTPS2DQ xmm1, xmm2/m128 VEX.128.F3.0F.WIG 5B /r
VCVTTPS2DQ ymm1, ymm2/m256 VEX.256.F3.0F.WIG 5B /r
VCVTTPS2DQ xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.F3.0F.W0 5B /r
VCVTTPS2DQ ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.F3.0F.W0 5B /r
VCVTTPS2DQ zmm1 {k1}{z}, zmm2/m512/m32bcst {sae} EVEX.512.F3.0F.W0 5B /r
Category
sse2,pcksp
Operands
Vdq,Wps
Opcode
0xF30F5B /r
CPU
P4+
Tested by
t5224 
IizVCVTTPS2DQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowSuppressing
    IiEmitOpcode 0x5B
    IiEncoding DATA=DWORD
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.F3.0F.WIG, EVEX.128.F3.0F.W0
    RET
.ymm.mem:
.ymm.ymm:
    IiEmitPrefix VEX.256.F3.0F.WIG, EVEX.256.F3.0F.W0
    RET
.zmm.mem:
.zmm.zmm:    
    IiEmitPrefix EVEX.512.F3.0F.W0
    RET
  ENDP IizVCVTTPS2DQ::
↑ VCVTQQ2PS
Convert Packed Quadword Integers to Packed Single-Precision Floating-Point values
Intel reference
VCVTQQ2PS xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.0F.W1 5B /r
VCVTQQ2PS xmm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.0F.W1 5B /r
VCVTQQ2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.0F.W1 5B /r
Opcode
0x5B
Tested by
t5228 
IizVCVTQQ2PS:: PROC
    IiAllowModifier DATA,MASK
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x5B
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.mem:
    IiDispatchDataSize OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
    IiAbort '6793'  ; Please specify memory operand size with DATA=OWORD or DATA=YWORD.
.xmm.xmm:
    IiEmitPrefix EVEX.128.0F.W1
    RET
.xmm.ymm:
    IiEmitPrefix EVEX.256.0F.W1
    IiEncoding DATA=OWORD
    RET
.ymm.mem:
.ymm.zmm:
    IiEmitPrefix EVEX.512.0F.W1
    IiEncoding DATA=YWORD
    RET
  ENDP IizVCVTQQ2PS::
↑ VCVTSI2SS
Convert DWORD Integer to Scalar Single-FP Value
Intel reference
VCVTSI2SS xmm1, xmm2, r/m32 VEX.NDS.128.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m64 VEX.NDS.128.F3.0F.W1 2A /r
VCVTSI2SS xmm1, xmm2, r/m32{er} EVEX.NDS.LIG.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m64{er} EVEX.NDS.LIG.F3.0F.W1 2A /r
Category
sse1,conver
Operands
Vss,Edqp
Opcode
0xF30F2A /r
CPU
P3+
Tested by
t5222 
IizVCVTSI2SS:: PROC
    IiAllowModifier DATA
    IiEmitOpcode 0x2A
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.r32, xmm.xmm.r64, xmm.xmm.mem
.xmm.xmm.r32:
    IiAllowModifier ROUND
 .D:IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiEmitPrefix VEX.NDS.128.F3.0F.W0, EVEX.NDS.LIG.F3.0F.W0
    RET
.xmm.xmm.r64:
    IiAllowModifier ROUND
 .Q:JNSt [EDI+II.SssStatus],sssWidth64, .D:
    ; W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiEmitPrefix VEX.NDS.128.F3.0F.W1, EVEX.NDS.LIG.F3.0F.W1
    RET
.xmm.xmm.mem:
    IiDispatchDataSize DWORD=.D:, QWORD=.Q:
    IiAbort '6792'  ; Please specify memory operand size with DATA=DWORD or DATA=QWORD.
  ENDP IizVCVTSI2SS::
↑ VCVTSI2SD
Convert DW Integer to Scalar Double-FP Value
Intel reference
VCVTSI2SD xmm1, xmm2, r/m32 VEX.NDS.128.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m64 VEX.NDS.128.F2.0F.W1 2A /r
VCVTSI2SD xmm1, xmm2, r/m32 EVEX.NDS.LIG.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m64{er} EVEX.NDS.LIG.F2.0F.W1 2A /r
Category
sse2,pcksclr,conver
Operands
Vsd,Edqp
Opcode
0xF20F2A /r
CPU
P4+
Tested by
t5222 
IizVCVTSI2SD:: PROC
    IiAllowModifier DATA
    IiEmitOpcode 0x2A
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.r32, xmm.xmm.r64, xmm.xmm.mem
.xmm.xmm.r32:
    IiAllowModifier ROUND
 .D:IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiEmitPrefix VEX.NDS.128.F2.0F.W0, EVEX.NDS.LIG.F2.0F.W0
    RET
.xmm.xmm.r64:
    IiAllowModifier ROUND
 .Q:JNSt [EDI+II.SssStatus],sssWidth64, .D:
    ; W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiEmitPrefix VEX.NDS.128.F2.0F.W1, EVEX.NDS.LIG.F2.0F.W1
    RET
.xmm.xmm.mem:
    IiDispatchDataSize  DWORD=.D:, QWORD=.Q:
    IiAbort '6792'  ; Please specify memory operand size with DATA=DWORD or DATA=QWORD.
  ENDP IizVCVTSI2SD::
↑ VCVTSS2SI
Convert Scalar Single-FP Value to DWORD Integer
Intel reference
VCVTSS2SI r32, xmm1/m32 VEX.128.F3.0F.W0 2D /r
VCVTSS2SI r64, xmm1/m32 VEX.128.F3.0F.W1 2D /r
VCVTSS2SI r32, xmm1/m32{er} EVEX.LIG.F3.0F.W0 2D /r
VCVTSS2SI r64, xmm1/m32{er} EVEX.LIG.F3.0F.W1 2D /r
Category
sse1,conver
Operands
Gdqp,Wss
Opcode
0xF30F2D /r
CPU
P3+
Tested by
t5220 
IizVCVTSS2SI:: PROC
    IiAllowRounding Register=xmm
    IiEmitOpcode 0x2D
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEmitPrefix VEX.128.F3.0F.W0, EVEX.LIG.F3.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiAbortIfNot64
    IiEmitPrefix VEX.128.F3.0F.W1, EVEX.LIG.F3.0F.W1
    RET
  ENDP IizVCVTSS2SI::
↑ VCVTSD2SI
Convert Scalar Double-FP Value to DW Integer
Intel reference
VCVTSD2SI r32, xmm1/m64 VEX.128.F2.0F.W0 2D /r
VCVTSD2SI r64, xmm1/m64 VEX.128.F2.0F.W1 2D /r
VCVTSD2SI r32, xmm1/m64{er} EVEX.LIG.F2.0F.W0 2D /r
VCVTSD2SI r64, xmm1/m64{er} EVEX.LIG.F2.0F.W1 2D /r
Category
sse2,pcksclr,conver
Operands
Gdqp,Wsd
Opcode
0xF20F2D /r
CPU
P4+
Tested by
t5220 
IizVCVTSD2SI:: PROC
    IiAllowRounding Register=xmm
    IiEmitOpcode 0x2D
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.128.F2.0F.W0, EVEX.LIG.F2.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiAbortIfNot64
    IiEmitPrefix VEX.128.F2.0F.W1, EVEX.LIG.F2.0F.W1
    RET
  ENDP IizVCVTSD2SI::
↑ VCVTTSS2SI
Convert with Trunc. Scalar Single-FP Value to DW Integer
Intel reference
VCVTTSS2SI r32, xmm1/m32 VEX.128.F3.0F.W0 2C /r
VCVTTSS2SI r64, xmm1/m32 VEX.128.F3.0F.W1 2C /r
VCVTTSS2SI r32, xmm1/m32{sae} EVEX.LIG.F3.0F.W0 2C /r
VCVTTSS2SI r64, xmm1/m32{sae} EVEX.LIG.F3.0F.W1 2C /r
Category
sse1,conver
Operands
Gdqp,Wss
Opcode
0xF30F2C /r
CPU
P3+
Tested by
t5220 
IizVCVTTSS2SI:: PROC
    IiAllowSuppressing Register=xmm
    IiEmitOpcode 0x2C
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEmitPrefix VEX.128.F3.0F.W0, EVEX.LIG.F3.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiEncoding DATA=QWORD
    IiAbortIfNot64
    IiEmitPrefix VEX.128.F3.0F.W1, EVEX.LIG.F3.0F.W1
    RET
  ENDP IizVCVTTSS2SI::
↑ VCVTTSD2SI
Conv. with Trunc. Scalar Double-FP Value to Signed DW Int
Intel reference
VCVTTSD2SI r32, xmm1/m64 VEX.128.F2.0F.W0 2C /r
VCVTTSD2SI r64, xmm1/m64 VEX.128.F2.0F.W1 2C /r
VCVTTSD2SI r32, xmm1/m64{sae} EVEX.LIG.F2.0F.W0 2C /r
VCVTTSD2SI r64, xmm1/m64{sae} EVEX.LIG.F2.0F.W1 2C /r
Category
sse2,pcksclr,conver
Operands
Gdqp,Wsd
Opcode
0xF20F2C /r
CPU
P4+
Tested by
t5220 
IizVCVTTSD2SI:: PROC
    IiAllowSuppressing Register=xmm 
    IiEmitOpcode 0x2C
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.128.F2.0F.W0, EVEX.LIG.F2.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiAbortIfNot64
    IiEmitPrefix VEX.128.F2.0F.W1, EVEX.LIG.F2.0F.W1
    RET
  ENDP IizVCVTTSD2SI::
↑ VCVTSS2USI
Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword
Intel reference
VCVTSS2USI r32, xmm1/m32{er} EVEX.LIG.F3.0F.W0 79 /r
VCVTSS2USI r64, xmm1/m32{er} EVEX.LIG.F3.0F.W1 79 /r
Opcode
0x79
Tested by
t5220 
IizVCVTSS2USI:: PROC
    IiAllowRounding Register=xmm
    IiEmitOpcode 0x79
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEmitPrefix EVEX.LIG.F3.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiEncoding DATA=QWORD
    IiAbortIfNot64
    IiEmitPrefix EVEX.LIG.F3.0F.W1
    RET
  ENDP IizVCVTSS2USI::
↑ VCVTSD2USI
Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer
Intel reference
VCVTSD2USI r32, xmm1/m64{er} EVEX.LIG.F2.0F.W0 79 /r
VCVTSD2USI r64, xmm1/m64{er} EVEX.LIG.F2.0F.W1 79 /r
Opcode
0x79
Tested by
t5220 
IizVCVTSD2USI:: PROC
    IiAllowRounding Register=xmm
    IiEmitOpcode 0x79
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix EVEX.LIG.F2.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiAbortIfNot64
    IiEmitPrefix EVEX.LIG.F2.0F.W1
    RET
  ENDP IizVCVTSD2USI::
↑ VCVTTSS2USI
Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer
Intel reference
VCVTTSS2USI r32, xmm1/m32{sae} EVEX.LIG.F3.0F.W0 78 /r
VCVTTSS2USI r64, xmm1/m32{sae} EVEX.LIG.F3.0F.W1 78 /r
Opcode
0x78
Tested by
t5220 
IizVCVTTSS2USI:: PROC
    IiAllowSuppressing Register=xmm
    IiEmitOpcode 0x78
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEmitPrefix EVEX.LIG.F3.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiEncoding DATA=QWORD
    IiAbortIfNot64
    IiEmitPrefix EVEX.LIG.F3.0F.W1
    RET
  ENDP IizVCVTTSS2USI::
↑ VCVTTSD2USI
Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer
Intel reference
VCVTTSD2USI r32, xmm1/m64{sae} EVEX.LIG.F2.0F.W0 78 /r
VCVTTSD2USI r64, xmm1/m64{sae} EVEX.LIG.F2.0F.W1 78 /r
Opcode
0x87
Tested by
t5220 
IizVCVTTSD2USI:: PROC
    IiAllowSuppressing Register=xmm
    IiEmitOpcode 0x78
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix EVEX.LIG.F2.0F.W0
    RET
.r64.xmm:
.r64.mem:
    IiAbortIfNot64
    IiEmitPrefix EVEX.LIG.F2.0F.W1
    RET
  ENDP IizVCVTTSD2USI::
↑ VCVTUSI2SS
Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value
Intel reference
VCVTUSI2SS xmm1, xmm2, r/m32{er} EVEX.NDS.LIG.F3.0F.W0 7B /r
VCVTUSI2SS xmm1, xmm2, r/m64{er} EVEX.NDS.LIG.F3.0F.W1 7B /r
Opcode
0x7B
Tested by
t5222 
IizVCVTUSI2SS:: PROC
    IiEmitOpcode 0x7B
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.r32, xmm.xmm.r64, xmm.xmm.mem
.xmm.xmm.r32:
    IiAllowModifier ROUND
 .D:IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiEmitPrefix EVEX.NDS.LIG.F3.0F.W0
    RET
.xmm.xmm.r64:
    IiAllowModifier ROUND
 .Q:IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiEmitPrefix EVEX.NDS.LIG.F3.0F.W1
    RET
.xmm.xmm.mem:
    IiAllowModifier DATA
    IiDispatchDataSize DWORD=.D:, QWORD=.Q:
    IiAbort '6792'  ; Please specify memory operand size with DATA=DWORD or DATA=QWORD.
  ENDP IizVCVTUSI2SS::
↑ VCVTUSI2SD
Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value
Intel reference
VCVTUSI2SD xmm1, xmm2, r/m32 EVEX.NDS.LIG.F2.0F.W0 7B /r
VCVTUSI2SD xmm1, xmm2, r/m64{er} EVEX.NDS.LIG.F2.0F.W1 7B /r
Opcode
0x7B
Tested by
t5222 
IizVCVTUSI2SD:: PROC
    IiEmitOpcode 0x7B
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.r32, xmm.xmm.r64, xmm.xmm.mem
.xmm.xmm.r32:
    IiAllowModifier ROUND
 .D:IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiEmitPrefix EVEX.NDS.LIG.F2.0F.W0
    RET
.xmm.xmm.r64:
    IiAllowModifier ROUND
 .Q:IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiEmitPrefix EVEX.NDS.LIG.F2.0F.W1
    RET
.xmm.xmm.mem:
    IiAllowModifier DATA
    IiDispatchDataSize DWORD=.D:, QWORD=.Q:
    IiAbort '6792'  ; Please specify memory operand size with DATA=DWORD or DATA=QWORD.
  ENDP IizVCVTUSI2SD::
↑ VCVTUDQ2PS
Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values
Intel reference
VCVTUDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.F2.0F.W0 7A /r
VCVTUDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.F2.0F.W0 7A /r
VCVTUDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er} EVEX.512.F2.0F.W0 7A /r
Opcode
0x7A
Tested by
t5228 
IizVCVTUDQ2PS:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowRounding
    IiEmitOpcode 0x7A
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix EVEX.128.F2.0F.W0
    RET
.ymm.mem:
.ymm.ymm:
    IiEmitPrefix EVEX.256.F2.0F.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F2.0F.W0
    RET
  ENDP IizVCVTUDQ2PS::
↑ VCVTUDQ2PD
Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values
Intel reference
VCVTUDQ2PD xmm1 {k1}{z}, xmm2/m64/m32bcst EVEX.128.F3.0F.W0 7A /r
VCVTUDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst EVEX.256.F3.0F.W0 7A /r
VCVTUDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst EVEX.512.F3.0F.W0 7A /r
VCVTUDQ2PD zmm1 {k1}, zmm2/m256/m32bcst MVEX.512.F3.0F.W0 7A /r
Opcode
0x7A
Tested by
t5230 
IizVCVTUDQ2PD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiEmitOpcode 0x7A
    IiDisp8EVEX HV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem, zmm.zmm
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix EVEX.128.F3.0F.W0
    IiEncoding DATA=QWORD
    RET
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix EVEX.256.F3.0F.W0
    IiEncoding DATA=OWORD
    RET
.zmm.ymm:
    IiEmitPrefix EVEX.512.F3.0F.W0
    IiEncoding DATA=YWORD
    RET
.zmm.mem:
    JNSt [EDI+II.MfxExplicit],iiMfxPREFIX_MVEX, .zmm.ymm:
    IiDisp8MVEX Sb32
.zmm.zmm:
    IiEmitPrefix MVEX.512.F3.0F.W0
    IiEncoding DATA=YWORD
    RET
  ENDP IizVCVTUDQ2PD::
↑ VCVTTPS2UDQ
Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Intel reference
VCVTTPS2UDQ xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.0F.W0 78 /r
VCVTTPS2UDQ ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.0F.W0 78 /r
VCVTTPS2UDQ zmm1 {k1}{z}, zmm2/m512/m32bcst{sae} EVEX.512.0F.W0 78 /r
Opcode
0x78
Tested by
t5224 
IizVCVTTPS2UDQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowSuppressing
    IiEmitOpcode 0x78
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:    
.xmm.xmm:
    IiEmitPrefix EVEX.128.0F.W0
    RET
.ymm.mem:
.ymm.ymm:
    IiEmitPrefix EVEX.256.0F.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.0F.W0
    RET
  ENDP IizVCVTTPS2UDQ::
↑ VCVTTPD2UDQ
Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Intel reference
VCVTTPD2UDQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.0F.W1 78 /r
VCVTTPD2UDQ xmm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.0F.W1 78 02 /r
VCVTTPD2UDQ ymm1 {k1}{z}, zmm2/m512/m64bcst{sae} EVEX.512.0F.W1 78 /r
Opcode
0x78
Tested by
t5224 
IizVCVTTPD2UDQ:: PROC
    IiAllowModifier MASK,DATA
    IiAllowBroadcasting QWORD
    IiAllowSuppressing
    IiEmitOpcode 0x78
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.xmm:
    IiEmitPrefix EVEX.128.0F.W1
    RET
.xmm.ymm:
    IiEmitPrefix EVEX.256.0F.W1
    RET
.ymm.zmm:
.ymm.mem:
    IiEmitPrefix EVEX.512.0F.W1
    RET
.xmm.mem:
    IiDispatchDataSize OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
    IiAbort '6793'  ; Please specify memory operand size with DATA=OWORD or DATA=YWORD.
  ENDP IizVCVTTPD2UDQ::
↑ VCVTTPS2UQQ
Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Intel reference
VCVTTPS2UQQ xmm1 {k1}{z}, xmm2/m64/m32bcst EVEX.128.66.0F.W0 78 /r
VCVTTPS2UQQ ymm1 {k1}{z}, xmm2/m128/m32bcst EVEX.256.66.0F.W0 78 /r
VCVTTPS2UQQ zmm1 {k1}{z}, ymm2/m256/m32bcst{sae} EVEX.512.66.0F.W0 78 /r
Opcode
0x78
Tested by
t5226 
IizVCVTTPS2UQQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowSuppressing Register=ymm
    IiEmitOpcode 0x78
    IiDisp8EVEX HV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W0
    RET
.ymm.xmm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W0
    RET
.zmm.ymm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W0
    RET
  ENDP IizVCVTTPS2UQQ::
↑ VCVTTPD2UQQ
Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
Intel reference
VCVTTPD2UQQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F.W1 78 /r
VCVTTPD2UQQ ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F.W1 78 /r
VCVTTPD2UQQ zmm1 {k1}{z}, zmm2/m512/m64bcst{sae} EVEX.512.66.0F.W1 78 /r
Opcode
0x78
Tested by
t5226 
IizVCVTTPD2UQQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowSuppressing
    IiEmitOpcode 0x78
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1
    RET
  ENDP IizVCVTTPD2UQQ::
↑ VCVTPS2UDQ
Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
Intel reference
VCVTPS2UDQ xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.0F.W0 79 /r
VCVTPS2UDQ ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.0F.W0 79 /r
VCVTPS2UDQ zmm1 {k1}{z}, zmm2/m512/m32bcst{er} EVEX.512.0F.W0 79 /r
Opcode
0x79
Tested by
t5224 
IizVCVTPS2UDQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowRounding
    IiEmitOpcode 0x79
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.0F.W0
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.0F.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.0F.W0
    RET
  ENDP IizVCVTPS2UDQ::
↑ VCVTPD2UDQ
Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Intel reference
VCVTPD2UDQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.0F.W1 79 /r
VCVTPD2UDQ xmm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.0F.W1 79 /r
VCVTPD2UDQ ymm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.0F.W1 79 /r
Opcode
0x79
Tested by
t5224 
IizVCVTPD2UDQ:: PROC
    IiAllowModifier MASK,DATA
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode 0x79
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.xmm:
    IiEmitPrefix EVEX.128.0F.W1
    IiEncoding DATA=QWORD
    RET
.xmm.ymm:
    IiEmitPrefix EVEX.256.0F.W1
    IiEncoding DATA=OWORD
    RET
.ymm.zmm:
.ymm.mem:
    IiEmitPrefix EVEX.512.0F.W1
    IiEncoding DATA=YWORD
    RET
.xmm.mem:
    IiDispatchDataSize OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
    IiAbort '6793'  ; Please specify memory operand size with DATA=OWORD or DATA=YWORD.
  ENDP IizVCVTPD2UDQ::
↑ VCVTPS2UQQ
Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Intel reference
VCVTPS2UQQ xmm1 {k1}{z}, xmm2/m64/m32bcst EVEX.128.66.0F.W0 79 /r
VCVTPS2UQQ ymm1 {k1}{z}, xmm2/m128/m32bcst EVEX.256.66.0F.W0 79 /r
VCVTPS2UQQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er} EVEX.512.66.0F.W0 79 /r
Opcode
0x79
Tested by
t5226 
IizVCVTPS2UQQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowRounding Register=ymm
    IiEmitOpcode 0x79
    IiDisp8EVEX HV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W0
    IiEncoding DATA=QWORD
    RET
.ymm.xmm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W0
    IiEncoding DATA=OWORD
    RET
.zmm.ymm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W0
    IiEncoding DATA=YWORD
    RET
  ENDP IizVCVTPS2UQQ::
↑ VCVTTPS2QQ
Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
Intel reference
VCVTTPS2QQ xmm1 {k1}{z}, xmm2/m64/m32bcst EVEX.128.66.0F.W0 7A /r
VCVTTPS2QQ ymm1 {k1}{z}, xmm2/m128/m32bcst EVEX.256.66.0F.W0 7A /r
VCVTTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{sae} EVEX.512.66.0F.W0 7A /r
Opcode
0x7A
Tested by
t5226 
IizVCVTTPS2QQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowSuppressing Register=ymm
    IiEmitOpcode 0x7A
    IiDisp8EVEX HV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W0
    IiEncoding DATA=QWORD
    RET
.ymm.xmm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W0
    IiEncoding DATA=OWORD
    RET
.zmm.ymm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W0
    IiEncoding DATA=YWORD
    RET
  ENDP IizVCVTTPS2QQ::
↑ VCVTPS2QQ
Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values
Intel reference
VCVTPS2QQ xmm1 {k1}{z}, xmm2/m64/m32bcst EVEX.128.66.0F.W0 7B /r
VCVTPS2QQ ymm1 {k1}{z}, xmm2/m128/m32bcst EVEX.256.66.0F.W0 7B /r
VCVTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er} EVEX.512.66.0F.W0 7B /r
Opcode
0x7B
Tested by
t5226 
IizVCVTPS2QQ:: PROC
  IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowRounding Register=ymm
    IiEmitOpcode 0x7B
    IiDisp8EVEX HV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W0
    IiEncoding DATA=QWORD
    RET
.ymm.xmm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W0
    IiEncoding DATA=OWORD
    RET
.zmm.ymm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W0
    IiEncoding DATA=YWORD
    RET
  ENDP IizVCVTPS2QQ::
↑ VCVTTPD2QQ
Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers
Intel reference
VCVTTPD2QQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F.W1 7A /r
VCVTTPD2QQ ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F.W1 7A /r
VCVTTPD2QQ zmm1 {k1}{z}, zmm2/m512/m64bcst{sae} EVEX.512.66.0F.W1 7A /r
Opcode
0x7A
Tested by
t5226 
IizVCVTTPD2QQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowSuppressing
    IiEmitOpcode 0x7A
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1
    RET
  ENDP IizVCVTTPD2QQ::
↑ VCVTPD2UQQ
Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers
Intel reference
VCVTPD2UQQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F.W1 79 /r
VCVTPD2UQQ ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F.W1 79 /r
VCVTPD2UQQ zmm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.66.0F.W1 79 /r
Opcode
0x79
Tested by
t5226 
IizVCVTPD2UQQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode 0x79
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1
    RET
  ENDP IizVCVTPD2UQQ::
↑ VCVTPD2QQ
Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers
Intel reference
VCVTPD2QQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F.W1 7B /r
VCVTPD2QQ ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F.W1 7B /r
VCVTPD2QQ zmm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.66.0F.W1 7B /r
Opcode
0x7B
Tested by
t5226 
IizVCVTPD2QQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode 0x7B
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1
    RET
  ENDP IizVCVTPD2QQ::
↑ VCVTTPD2DQ
Convert with Trunc. Packed Double-FP Values to DW Integers
Intel reference
VCVTTPD2DQ xmm1, xmm2/m128 VEX.128.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1, ymm2/m256 VEX.256.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F.W1 E6 /r
VCVTTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F.W1 E6 /r
VCVTTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{sae} EVEX.512.66.0F.W1 E6 /r
Category
sse2,pcksclr,conver
Operands
Vdq,Wpd
Opcode
0x660FE6 /r
CPU
P4+
Tested by
t5224 
IizVCVTTPD2DQ:: PROC
    IiAllowModifier MASK,DATA
    IiAllowBroadcasting QWORD
    IiAllowSuppressing
    IiEmitOpcode 0xE6
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
    IiEncoding DATA=QWORD
    RET
.xmm.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W1
    IiEncoding DATA=OWORD
    RET
.ymm.zmm:
.ymm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1
    IiEncoding DATA=YWORD
    RET
.xmm.mem:
    IiDispatchDataSize OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
    IiAbort '6793'  ; Please specify memory operand size with DATA=OWORD or DATA=YWORD.
  ENDP IizVCVTTPD2DQ::
↑ VCVTPD2DQ
Convert Packed Double-FP Values to DW Integers
Intel reference
VCVTPD2DQ xmm1, xmm2/m128 VEX.128.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1, ymm2/m256 VEX.256.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.F2.0F.W1 E6 /r
VCVTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.F2.0F.W1 E6 /r
VCVTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.F2.0F.W1 E6 /r
Category
sse2,pcksclr,conver
Operands
Vdq,Wpd
Opcode
0xF20FE6 /r
CPU
P4+
Tested by
t5224 
IizVCVTPD2DQ:: PROC
    IiAllowModifier MASK,DATA
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode 0xE6
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.xmm:
    IiEmitPrefix VEX.128.F2.66.0F.WIG, EVEX.128.F2.66.0F.W1
    IiEncoding DATA=QWORD
    RET
.xmm.ymm:
    IiEmitPrefix VEX.256.F2.66.0F.WIG, EVEX.256.F2.66.0F.W1
    IiEncoding DATA=OWORD
    RET
.ymm.zmm:
.ymm.mem:
    IiEmitPrefix EVEX.512.F2.66.0F.W1
    IiEncoding DATA=YWORD
    RET
.xmm.mem:
    IiDispatchDataSize OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
    IiAbort '6793'  ; Please specify memory operand size with DATA=OWORD or DATA=YWORD.
  ENDP IizVCVTPD2DQ::
↑ VCVTDQ2PD
Convert Packed DW Integers to Double-FP Values
Intel reference
VCVTDQ2PD xmm1, xmm2/m64 VEX.128.F3.0F.WIG E6 /r
VCVTDQ2PD ymm1, xmm2/m128 VEX.256.F3.0F.WIG E6 /r
VCVTDQ2PD xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.F3.0F.W0 E6 /r
VCVTDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst EVEX.256.F3.0F.W0 E6 /r
VCVTDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst EVEX.512.F3.0F.W0 E6 /r
VCVTDQ2PD zmm1 {k1}, zmm2/m256/m32bcst MVEX.512.F3.0F.W0 E6 /r
Category
sse2,pcksclr,conver
Operands
Vpd,Wdq
Opcode
0xF30FE6 /r
CPU
P4+
Tested by
t5230 
IizVCVTDQ2PD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiEmitOpcode 0xE6
    IiDisp8EVEX HV32
    IiDisp8MVEX Sb32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem, zmm.zmm
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.F3.0F.WIG, EVEX.128.F3.0F.W0
    RET
.ymm.xmm:
.ymm.mem:
    IiEmitPrefix VEX.256.F3.0F.WIG, EVEX.256.F3.0F.W0
    RET
.zmm.ymm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F3.0F.W0, MVEX.512.F3.0F.W0
    RET
.zmm.zmm:
    IiEmitPrefix MVEX.512.F3.0F.W0
    RET
  ENDP IizVCVTDQ2PD::
↑ VCVTQQ2PD
Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values
Intel reference
VCVTQQ2PD xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.F3.0F.W1 E6 /r
VCVTQQ2PD ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.F3.0F.W1 E6 /r
VCVTQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.F3.0F.W1 E6 /r
Opcode
0xE6
Tested by
t5230 
IizVCVTQQ2PD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode 0xE6
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.F3.0F.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.F3.0F.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F3.0F.W1
    RET
  ENDP IizVCVTQQ2PD::
↑ VCVTUQQ2PS
Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values
Intel reference
VCVTUQQ2PS xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.F2.0F.W1 7A /r
VCVTUQQ2PS xmm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.F2.0F.W1 7A /r
VCVTUQQ2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.F2.0F.W1 7A /r
Opcode
0x7A
Tested by
t5228 
IizVCVTUQQ2PS:: PROC
    IiAllowModifier MASK,DATA
    IiAllowBroadcasting QWORD
    IiAllowRounding
    IiEmitOpcode 0x7A
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.xmm:
    IiEmitPrefix EVEX.128.F2.0F.W1
    RET
.xmm.ymm:
    IiEmitPrefix EVEX.256.F2.0F.W1
    RET
.ymm.mem:
.ymm.zmm:
    IiEmitPrefix EVEX.512.F2.0F.W1
    RET
.xmm.mem:
    IiDispatchDataSize OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
    IiAbort '6793'  ; Please specify memory operand size with DATA=OWORD or DATA=YWORD.
  ENDP IizVCVTUQQ2PS::
↑ VCVTUQQ2PD
Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values
Intel reference
VCVTUQQ2PD xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.F3.0F.W1 7A /r
VCVTUQQ2PD ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.F3.0F.W1 7A /r
VCVTUQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst{er} EVEX.512.F3.0F.W1 7A /r
Opcode
0x7A
Tested by
t5230 
IizVCVTUQQ2PD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowRounding 
    IiEmitOpcode 0x7A
    IiDisp8EVEX FV64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.F3.0F.W1
    RET
.ymm.mem:
.ymm.ymm:
    IiEmitPrefix EVEX.256.F3.0F.W1
    RET
.zmm.mem:
.zmm.zmm:
    IiEmitPrefix EVEX.512.F3.0F.W1
    RET
  ENDP IizVCVTUQQ2PD::
↑ VCVTPH2PS
Convert 16-bit FP values to Single-Precision FP values
Description
VCVTPH2PS
Intel reference
VCVTPH2PS xmm1, xmm2/m64 VEX.128.66.0F38.W0 13 /r
VCVTPH2PS ymm1, xmm2/m128 VEX.256.66.0F38.W0 13 /r
VCVTPH2PS xmm1 {k1}{z}, xmm2/m64 EVEX.128.66.0F38.W0 13 /r
VCVTPH2PS ymm1 {k1}{z}, xmm2/m128 EVEX.256.66.0F38.W0 13 /r
VCVTPH2PS zmm1 {k1}{z}, ymm2/m256 {sae} EVEX.512.66.0F38.W0 13 /r
Opcode
0x13
Tested by
t5228 
IizVCVTPH2PS:: PROC
    IiRequire SPEC
    IiAllowModifier MASK
    IiAllowSuppressing Register=ymm 
    IiEmitOpcode 0x13
    IiEncoding DATA=WORD
    IiDisp8EVEX HVM
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
    RET
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
    RET
.zmm.ymm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
  ENDP IizVCVTPH2PS::
↑ VCVTPS2PH
Convert Single-Precision FP value to 16-bit FP value
Description
VCVTPS2PH
Intel reference
VCVTPS2PH xmm1/m64, xmm2, imm8 VEX.128.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m128, ymm2, imm8 VEX.256.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m64 {k1}{z}, xmm2, imm8 EVEX.128.66.0F3A.W0 1D /r ib
VCVTPS2PH xmm1/m128 {k1}{z}, ymm2, imm8 EVEX.256.66.0F3A.W0 1D /r ib
VCVTPS2PH ymm1/m256 {k1}{z}, zmm2{sae}, imm8 EVEX.512.66.0F3A.W0 1D /r ib
Operands
0x1D
Tested by
t5230 
IizVCVTPS2PH:: PROC
    IiRequire SPEC
    IiAllowModifier MASK,DATA
    IiAllowSuppressing Operand=DH
    IiEmitOpcode 0x1D
    IiEncoding DATA=WORD
    IiDisp8EVEX HVM
    IiEmitImm Operand3, BYTE
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat  xmm.xmm.imm, mem.xmm.imm, xmm.ymm.imm, mem.ymm.imm, ymm.zmm.imm, mem.zmm.imm
.mem.xmm.imm:
.xmm.xmm.imm:
    IiEmitPrefix VEX.128.66.0F3A.W0, EVEX.128.66.0F3A.W0
    RET
.mem.ymm.imm:
.xmm.ymm.imm:
    IiEmitPrefix VEX.256.66.0F3A.W0, EVEX.256.66.0F3A.W0
    RET
.ymm.zmm.imm:
    IiAllowModifier SAE
.mem.zmm.imm:
    IiEmitPrefix EVEX.512.66.0F3A.W0
    RET
  ENDP IizVCVTPS2PH::
↑ VBROADCASTSS
Load with Broadcast Floating-Point Data Scalar float32
Intel reference
VBROADCASTSS xmm1, m32 VEX.128.66.0F38.W0 18 /r
VBROADCASTSS ymm1, m32 VEX.256.66.0F38.W0 18 /r
VBROADCASTSS xmm1 {k1}{z}, xmm2/m32 EVEX.128.66.0F38.W0 18 /r
VBROADCASTSS ymm1 {k1}{z}, xmm2/m32 EVEX.256.66.0F38.W0 18 /r
VBROADCASTSS zmm1 {k1}{z}, xmm2/m32 EVEX.512.66.0F38.W0 18 /r
VBROADCASTSS zmm1 {k1}, m32 MVEX.512.66.0F38.W0 18 /r
Opcode
0x18
Tested by
t5240 
IizVBROADCASTSS:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x18
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.mem, ymm.mem, xmm.xmm, ymm.xmm, zmm.xmm, zmm.mem
.xmm.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
.ymm.xmm:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.zmm.xmm:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
    RET
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
    RET
.zmm.mem:
    IiDisp8MVEX Df32
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    RET
  ENDP IizVBROADCASTSS::
↑ VBROADCASTSD
Load with Broadcast Floating-Point Data Scalar float64
Intel reference
VBROADCASTSD ymm1, m64 VEX.256.66.0F38.W0 19 /r
VBROADCASTSD ymm1 {k1}{z}, xmm2/m64 EVEX.256.66.0F38.W1 19 /r
VBROADCASTSD zmm1 {k1}{z}, xmm2/m64 EVEX.512.66.0F38.W1 19 /r
VBROADCASTSD zmm1 {k1}, mem MVEX.512.66.0F38.W1 19 /r
Opcode
0x19
Tested by
t5240 
IizVBROADCASTSD:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x19
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  ymm.mem, ymm.xmm, zmm.xmm, zmm.mem
.ymm.xmm:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.zmm.xmm:
    IiEmitPrefix EVEX.512.66.0F38.W1
    RET
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W1
    RET
.zmm.mem:
    IiDisp8MVEX Sn64
    IiEmitPrefix EVEX.512.66.0F38.W1, MVEX.512.66.0F38.W1
    RET
  ENDP IizVBROADCASTSD::
↑ VBROADCASTF128
Load with Broadcast Floating-Point Data Scalar float128
Intel reference
VBROADCASTF128 ymm1, m128 VEX.256.66.0F38.W0 1A /r
Opcode
0x1A
Tested by
t5240 
IizVBROADCASTF128:: PROC
    IiEncoding DATA=OWORD
    IiEmitOpcode 0x1A
    IiOpEn RM
    IiModRM /r
    IiEmitPrefix VEX.256.66.0F38.W0
    IiDispatchFormat  ymm.mem
.ymm.mem:
    RET
  ENDP IizVBROADCASTF128::
↑ VBROADCASTF32X2
Load with Broadcast Floating-Point Data two float32
Intel reference
VBROADCASTF32X2 ymm1 {k1}{z}, xmm2/m64 EVEX.256.66.0F38.W0 19 /r
VBROADCASTF32X2 zmm1 {k1}{z}, xmm2/m64 EVEX.512.66.0F38.W0 19 /r
Opcode
0x19
Tested by
t5242 
IizVBROADCASTF32X2:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x19
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  ymm.xmm, ymm.mem, zmm.xmm, zmm.mem
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.zmm.mem:
.zmm.xmm:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
  ENDP IizVBROADCASTF32X2::
↑ VBROADCASTF32X4
Load with Broadcast Floating-Point Data four float32
Intel reference
VBROADCASTF32X4 ymm1 {k1}{z}, m128 EVEX.256.66.0F38.W0 1A /r
VBROADCASTF32X4 zmm1 {k1}{z}, m128 EVEX.512.66.0F38.W0 1A /r
VBROADCASTF32X4 zmm1 {k1}, mem MVEX.512.66.0F38.W0 1A /r
Opcode
0x1A
Tested by
t5242 
IizVBROADCASTF32X4:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiDisp8EVEX T2F64
    IiDisp8MVEX Sn32
    IiEmitOpcode 0x1A
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  ymm.mem, zmm.mem
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    RET
  ENDP IizVBROADCASTF32X4::
↑ VBROADCASTF32X8
Load with Broadcast Floating-Point Data eight float32
Intel reference
VBROADCASTF32X8 zmm1 {k1}{z}, m256EVEX.512.66.0F38.W0 1B /r
Opcode
0x1B
Tested by
t5242 
IizVBROADCASTF32X8:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x1B
    IiDisp8EVEX T4F64
    IiOpEn RM
    IiModRM /r
    IiEmitPrefix EVEX.512.66.0F38.W0
    IiDispatchFormat  zmm.mem
.zmm.mem:
    RET
  ENDP IizVBROADCASTF32X8::
↑ VBROADCASTF64X2
Load with Broadcast Floating-Point Data two float64
Intel reference
VBROADCASTF64X2 ymm1 {k1}{z}, m128 EVEX.256.66.0F38.W1 1A /r
VBROADCASTF64X2 zmm1 {k1}{z}, m128EVEX.512.66.0F38.W1 1A /r
Opcode
0x1A
Tested by
t5242 
IizVBROADCASTF64X2:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x1A
    IiDisp8EVEX T2F64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  ymm.mem, zmm.mem
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W1
    RET
  ENDP IizVBROADCASTF64X2::
↑ VBROADCASTF64X4
Load with Broadcast Floating-Point Data four float64
Intel reference
VBROADCASTF64X4 zmm1 {k1}{z}, m256 EVEX.512.66.0F38.W1 1B /r
VBROADCASTF64X4 zmm1 {k1}, memMVEX.512.66.0F38.W1 1B /r
Opcode
0x1B
Tested by
t5242 
IizVBROADCASTF64X4:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x1B
    IiDisp8EVEX T4F64
    IiDisp8MVEX Si64
    IiOpEn RM
    IiModRM /r
    IiEmitPrefix EVEX.512.66.0F38.W1, MVEX.512.66.0F38.W1
    IiDispatchFormat  zmm.mem
.zmm.mem:
    RET
  ENDP IizVBROADCASTF64X4::
↑ VBROADCASTI32X4
Broadcast 4xInt32 Vector
Intel reference
VBROADCASTI32X4 ymm1 {k1}{z}, m128 EVEX.256.66.0F38.W0 5A /r
VBROADCASTI32X4 zmm1 {k1}{z}, m128 EVEX.512.66.0F38.W0 5A /r
VBROADCASTI32X4 zmm1 {k1}, mem MVEX.512.66.0F38.W0 5A /r
Opcode
0x5A
Tested by
t5244 
IizVBROADCASTI32X4:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x5A
    IiDisp8EVEX T2F64
    IiDisp8MVEX Ui32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  ymm.mem, zmm.mem
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    RET
  ENDP IizVBROADCASTI32X4::
↑ VBROADCASTI64X4
Broadcast 4xInt64 Vector
Intel reference
VBROADCASTI64X4 zmm1 {k1}{z}, mem EVEX.512.66.0F38.W1 5B /r
VBROADCASTI64X4 zmm1 {k1}, mem MVEX.512.66.0F38.W1 5B /r
Opcode
0x5B
Tested by
t5244 
IizVBROADCASTI64X4:: PROC
    IiAllowModifier MASK     
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x5B
    IiDisp8EVEX T4F64
    IiDisp8MVEX Si64
    IiOpEn RM
    IiModRM /r
    IiEmitPrefix EVEX.512.66.0F38.W1, MVEX.512.66.0F38.W1
    IiDispatchFormat  zmm.mem
.zmm.mem:
    RET
  ENDP IizVBROADCASTI64X4::
↑ VBROADCASTI32X2
Load Integer and Broadcast two int32
Intel reference
VBROADCASTI32X2 xmm1 {k1}{z}, xmm2/m64 EVEX.128.66.0F38.W0 59 /r
VBROADCASTI32X2 ymm1 {k1}{z}, xmm2/m64 EVEX.256.66.0F38.W0 59 /r
VBROADCASTI32X2 zmm1 {k1}{z}, xmm2/m64EVEX.512.66.0F38.W0 59 /r
Opcode
0x59
Tested by
t5244 
IizVBROADCASTI32X2:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x59
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.zmm.mem:
.zmm.xmm:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
  ENDP IizVBROADCASTI32X2::
↑ VBROADCASTI128
Load Integer and Broadcast int128
Intel reference
VBROADCASTI128 ymm1, m128 VEX.256.66.0F38.W0 5A /r
Opcode
0x5A
Tested by
t5246 
IizVBROADCASTI128:: PROC
    IiEmitOpcode 0x5A
    IiEncoding DATA=OWORD
    IiOpEn RM
    IiModRM /r
    IiEmitPrefix VEX.256.66.0F38.W0
    IiDispatchFormat  ymm.mem
.ymm.mem:
    RET
  ENDP IizVBROADCASTI128::
↑ VBROADCASTI64X2
Load Integer and Broadcast two int64
Intel reference
VBROADCASTI64X2 ymm1 {k1}{z}, m128 EVEX.256.66.0F38.W1 5A /r
VBROADCASTI64X2 zmm1 {k1}{z}, m128 EVEX.512.66.0F38.W1 5A /r
Opcode
0x5A
Tested by
t5244 
IizVBROADCASTI64X2:: PROC
    IiAllowModifier MASK

    IiEncoding DATA=QWORD
    IiEmitOpcode 0x5A
    IiDisp8EVEX T2F64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  ymm.mem, zmm.mem
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W1
    RET
  ENDP IizVBROADCASTI64X2::
↑ VBROADCASTI32X8
Load Integer and Broadcast eight int32
Intel reference
VBROADCASTI32X8 zmm1 {k1}{z}, m256 EVEX.512.66.0F38.W1 5B /r
Opcode
0x5B
Tested by
t5244 
IizVBROADCASTI32X8:: PROC
    IiAllowModifier MASK
    IiEmitOpcode 0x5B
    IiDisp8EVEX T4F64
    IiEncoding DATA=DWORD
    IiOpEn RM
    IiModRM /r
    IiEmitPrefix EVEX.512.66.0F38.W0    
    IiDispatchFormat  zmm.mem
.zmm.mem:
    RET
  ENDP IizVBROADCASTI32X8::
↑ VPBROADCASTB
Load Integer and Broadcast sixteen int8
Intel reference
VPBROADCASTB xmm1 {k1}{z}, reg EVEX.128.66.0F38.W0 7A /r
VPBROADCASTB ymm1 {k1}{z}, reg EVEX.256.66.0F38.W0 7A /r
VPBROADCASTB zmm1 {k1}{z}, reg EVEX.512.66.0F38.W0 7A /r
VPBROADCASTB xmm1, xmm2/m8 VEX.128.66.0F38.W0 78 /r
VPBROADCASTB ymm1, xmm2/m8 VEX.256.66.0F38.W0 78 /r
VPBROADCASTB xmm1{k1}{z}, xmm2/m8 EVEX.128.66.0F38.W0 78 /r
VPBROADCASTB ymm1{k1}{z}, xmm2/m8 EVEX.256.66.0F38.W0 78 /r
VPBROADCASTB zmm1{k1}{z}, xmm2/m8 EVEX.512.66.0F38.W0 78 /r
Opcode
0x78 ||0x7A
Tested by
t5246 
IizVPBROADCASTB:: PROC
     IiAllowModifier MASK
     IiEncoding DATA=BYTE
     MOV AL,0x7A
     Dispatch DL,r8:,r16,r32,r64
     MOV AL,0x78
.r8:
.r16:
.r32:
.r64:IiEmitOpcode EAX
     IiDisp8EVEX T1S8
     IiOpEn RM
     IiModRM /r
     IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem, \
     xmm.r8, xmm.r16, xmm.r32, xmm.r64, \
     ymm.r8, ymm.r16, ymm.r32, ymm.r64, \
     zmm.r8, zmm.r16, zmm.r32, zmm.r64
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
    RET
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
    RET
.zmm.mem:
.zmm.xmm:
.zmm.r8:
.zmm.r16:
.zmm.r32:
.zmm.r64:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
.ymm.r8:
.ymm.r16:
.ymm.r32:
.ymm.r64:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.xmm.r8:
.xmm.r16:
.xmm.r32:
.xmm.r64:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
  ENDP IizVPBROADCASTB::
↑ VPBROADCASTW
Load Integer and Broadcast eight int16
Intel reference
VPBROADCASTW xmm1, xmm2/m16 VEX.128.66.0F38.W0 79 /r
VPBROADCASTW ymm1, xmm2/m16 VEX.256.66.0F38.W0 79 /r
VPBROADCASTW xmm1{k1}{z}, xmm2/m16 EVEX.128.66.0F38.W0 79 /r
VPBROADCASTW ymm1{k1}{z}, xmm2/m16 EVEX.256.66.0F38.W0 79 /r
VPBROADCASTW zmm1{k1}{z}, xmm2/m16 EVEX.512.66.0F38.W0 79 /r
VPBROADCASTW xmm1 {k1}{z}, reg EVEX.128.66.0F38.W0 7B /r
VPBROADCASTW ymm1 {k1}{z}, reg EVEX.256.66.0F38.W0 7B /r
VPBROADCASTW zmm1 {k1}{z}, reg EVEX.512.66.0F38.W0 7B /r
Opcode
0x79 || 0x7B
Tested by
t5246 
IizVPBROADCASTW:: PROC
     IiAllowModifier MASK
     IiEncoding DATA=WORD
     MOV AL,0x7B
     Dispatch DL,r16,r32,r64
     MOV AL,0x79
.r16:
.r32:
.r64:IiEmitOpcode EAX
     IiDisp8EVEX T1S16
     IiOpEn RM
     IiModRM /r
     IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem, \
     xmm.r16, xmm.r32, xmm.r64, \
     ymm.r16, ymm.r32, ymm.r64, \
     zmm.r16, zmm.r32, zmm.r64
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
    RET
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
    RET
.zmm.mem:
.zmm.xmm:
.zmm.r16:
.zmm.r32:
.zmm.r64:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
.ymm.r16:
.ymm.r32:
.ymm.r64:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.xmm.r16:
.xmm.r32:
.xmm.r64:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
  ENDP IizVPBROADCASTW::
↑ VPBROADCASTD
Load Integer and Broadcast int32
Intel reference
VPBROADCASTD xmm1, xmm2/m32 VEX.128.66.0F38.W0 58 /r
VPBROADCASTD ymm1, xmm2/m32 VEX.256.66.0F38.W0 58 /r
VPBROADCASTD xmm1 {k1}{z}, xmm2/m32 EVEX.128.66.0F38.W0 58 /r
VPBROADCASTD ymm1 {k1}{z}, xmm2/m32 EVEX.256.66.0F38.W0 58 /r
VPBROADCASTD zmm1 {k1}{z}, xmm2/m32 EVEX.512.66.0F38.W0 58 /r
VPBROADCASTD xmm1 {k1}{z}, r32 EVEX.128.66.0F38.W0 7C /r
VPBROADCASTD ymm1 {k1}{z}, r32 EVEX.256.66.0F38.W0 7C /r
VPBROADCASTD zmm1 {k1}{z}, r32 EVEX.512.66.0F38.W0 7C /r
Opcode
0x58 || 0x7C
Tested by
t5246 
IizVPBROADCASTD:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=DWORD
    MOV AL,0x7C
    Dispatch DL,r32,r64
    MOV AL,0x58
.r32:
.r64:IiEmitOpcode EAX
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem, \
     xmm.r32, xmm.r64, ymm.r32, ymm.r64, zmm.r32, zmm.r64:
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
    RET
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
    RET
.zmm.mem:
.zmm.xmm:
.zmm.r32:
.zmm.r64:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
.ymm.r32:
.ymm.r64:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.xmm.r32:
.xmm.r64:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
  ENDP IizVPBROADCASTD::
↑ VPBROADCASTQ
Load Integer and Broadcast int64
Intel reference
VPBROADCASTQ xmm1, xmm2/m64 VEX.128.66.0F38.W0 59 /r
VPBROADCASTQ ymm1, xmm2/m64 VEX.256.66.0F38.W0 59 /r
VPBROADCASTQ xmm1 {k1}{z}, xmm2/m64 EVEX.128.66.0F38.W1 59 /r
VPBROADCASTQ ymm1 {k1}{z}, xmm2/m64 EVEX.256.66.0F38.W1 59 /r
VPBROADCASTQ zmm1 {k1}{z}, xmm2/m64 EVEX.512.66.0F38.W1 59 /r
VPBROADCASTQ xmm1 {k1}{z}, r64 EVEX.128.66.0F38.W1 7C /r
VPBROADCASTQ ymm1 {k1}{z}, r64 EVEX.256.66.0F38.W1 7C /r
VPBROADCASTQ zmm1 {k1}{z}, r64 EVEX.512.66.0F38.W1 7C /r
Opcode
0x59||0x7C
Tested by
t5246 
IizVPBROADCASTQ:: PROC
     IiAllowModifier MASK
     IiEncoding DATA=QWORD
     MOV AL,0x7C
     Dispatch DL,r64
     MOV AL,0x59
.r64:IiEmitOpcode EAX
     IiDisp8EVEX T1S64
     IiOpEn RM
     IiModRM /r
     IiDispatchFormat  xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem, \
                       xmm.r64, ymm.r64, zmm.r64
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W1
    RET
.ymm.mem:
.ymm.xmm:
    IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W1
    RET
.zmm.mem:
.zmm.xmm:
.zmm.r64:
    IiEmitPrefix EVEX.512.66.0F38.W1
    RET
.ymm.r64:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.xmm.r64:
    IiEmitPrefix EVEX.128.66.0F38.W1
    RET
  ENDP IizVPBROADCASTQ::
↑ VALIGND
Align Doubleword Vectors
Intel reference
VALIGND xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst, imm8 EVEX.NDS.128.66.0F3A.W0 03 /r ib
VALIGND ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst, imm8 EVEX.NDS.256.66.0F3A.W0 03 /r ib
VALIGND zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst, imm8 EVEX.NDS.512.66.0F3A.W0 03 /r ib
VALIGND zmm1 {k1}{z}, zmm2, zmm3/m512/mem, imm8 MVEX.NDS.512.66.0F3A.W0 03 /r ib
Opcode
0x03
Tested by
t5250 
IizVALIGND:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD, Operand=DH
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x03
    IiDisp8EVEX FV32
    IiDisp8MVEX Si64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix EVEX.NDS.128.66.0F3A.W0
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W0
    RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W0, MVEX.NDS.512.66.0F3A.W0
    RET
  ENDP IizVALIGND::
↑ VALIGNQ
Align Quadword Vectors
Intel reference
VALIGNQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst, imm8 EVEX.NDS.128.66.0F3A.W1 03 /r ib
VALIGNQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst, imm8 EVEX.NDS.256.66.0F3A.W1 03 /r ib
VALIGNQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst, imm8 EVEX.NDS.512.66.0F3A.W1 03 /r ib
Opcode
0x03
Tested by
t5250 
IizVALIGNQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD, Operand=DH
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x03
    IiDisp8EVEX FV64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, \
                      ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix EVEX.NDS.128.66.0F3A.W1
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W1
    RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W1
    RET
  ENDP IizVALIGNQ::
↑ VPBLENDMB
Blend Byte Vectors Using an Opmask Control
Intel reference
VPBLENDMB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.W0 66 /r
VPBLENDMB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.W0 66 /r
VPBLENDMB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.W0 66 /r
Opcode
0x66
Tested by
t5252 
IizVPBLENDMB:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=BYTE
    IiEmitOpcode 0x66
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W0
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W0
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W0
    RET
  ENDP IizVPBLENDMB::
↑ VPBLENDMW
Blend Word Vectors Using an Opmask Control
Intel reference
VPBLENDMW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.W1 66 /r
VPBLENDMW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.W1 66 /r
VPBLENDMW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.W1 66 /r
Opcode
0x66
Tested by
t5252 
IizVPBLENDMW:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=WORD
    IiEmitOpcode 0x66
    IiDisp8EVEX FVM
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W1
    RET
  ENDP IizVPBLENDMW::
↑ VPBLENDMD
Blend Int32 Vectors Using an OpMask Control
Intel reference
VPBLENDMD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 64 /r
VPBLENDMD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 64 /r
VPBLENDMD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 64 /r
VPBLENDMD zmm1 {k1}, zmm2, zmm3/mem MVEX.NDS.512.66.0F38.W0 64 /r
Opcode
0x64
Tested by
t5252 
IizVPBLENDMD:: PROC
    IiAllowModifier MASK,EH
    IiAllowBroadcasting DWORD
    IiEmitOpcode 0x64
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV32
    IiDisp8MVEX Si32
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W0
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W0
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W0, MVEX.NDS.512.66.0F38.W0
    RET
  ENDP IizVPBLENDMD::
↑ VPBLENDMQ
Blend Int64 Vectors Using an OpMask Control
Intel reference
VPBLENDMQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 64 /r
VPBLENDMQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 64 /r
VPBLENDMQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 64 /r
VPBLENDMQ zmm1 {k1}, zmm2, zmm3/mem MVEX.NDS.512.66.0F38.W1 64 /r
Opcode
0x64
Tested by
t5252 
IizVPBLENDMQ:: PROC
    IiAllowModifier MASK,EH
    IiAllowBroadcasting QWORD
    IiEmitOpcode 0x64
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV64
    IiDisp8MVEX Ub64
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W1, MVEX.NDS.512.66.0F38.W1
    RET
  ENDP IizVPBLENDMQ::
↑ VBLENDMPS
Blend Float32 Vectors using the Instruction Mask
Intel reference
VBLENDMPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 65 /r
VBLENDMPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 65 /r
VBLENDMPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 65 /r
VBLENDMPS zmm1 {k1}, zmm2, zmm3/mem MVEX.NDS.512.66.0F38.W0 65 /r
Opcode
0x65
Tested by
t5254 
IizVBLENDMPS:: PROC
    IiAllowModifier MASK,EH
    IiAllowBroadcasting DWORD
    IiEmitOpcode 0x65
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV32
    IiDisp8MVEX Us32
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W0
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W0
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W0, MVEX.NDS.512.66.0F38.W0
    RET
  ENDP IizVBLENDMPS::
↑ VBLENDMPD
Blend Float64 Vectors Using the Instruction Mask
Intel reference
VBLENDMPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 65 /r
VBLENDMPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 65 /r
VBLENDMPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 65 /r
VBLENDMPD zmm1 {k1}, zmm2, zmm3/mem MVEX.NDS.512.66.0F38.W1 65 /r
Opcode
0x65
Tested by
t5254 
IizVBLENDMPD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiEmitOpcode 0x65
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV64
    IiDisp8MVEX Ub64
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W1, MVEX.NDS.512.66.0F38.W1
    RET
  ENDP IizVBLENDMPD::
↑ VCMPSS
Compare Scalar Single-FP Values
Intel reference
VCMPSS xmm1, xmm2, xmm3/m32, imm8 VEX.NDS.128.F3.0F.WIG C2 /r ib
VCMPSS k1 {k2}, xmm2, xmm3/m32{sae}, imm8 EVEX.NDS.LIG.F3.0F.W0 C2 /r ib
Operands
xmm/krg,xmm,xmm/mem,imm
Opcode
0xC2 /r ib
See also
VCMPSD VCMPPS VCMPPD
Tested by
t5260 
IizVCMPSS:: PROC
    IiAllowModifier MASK
    IiEmitOpcode 0xC2
    IiDisp8EVEX T1S32
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE, Max=31
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, krg.xmm.xmm.imm, krg.xmm.mem.imm
.cc: ; This entry is called with format xmm/krg,xmm,xmm/mem (no immediate).
    IiImmCreate CL
    JMP IizVCMPSS: ; Continue as if the condition were specified by imm value. 
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.F3.0F.WIG
    RET
.krg.xmm.xmm.imm:
    IiAllowModifier SAE
.krg.xmm.mem.imm:
    IiEmitPrefix EVEX.NDS.LIG.F3.0F.W0
    RET
  ENDP IizVCMPSS::
↑ VCMPEQSS
Compare Scalar Single-FP values Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQSS:: PROC
    MOV CL,0x00
    JMP IizVCMPSS.cc:
 ENDP IizVCMPEQSS::
↑ VCMPLTSS
Compare Scalar Single-FP values Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLTSS:: PROC
    MOV CL,0x01
    JMP IizVCMPSS.cc:
 ENDP IizVCMPLTSS::
↑ VCMPLESS
Compare Scalar Single-FP values Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLESS:: PROC
    MOV CL,0x02
    JMP IizVCMPSS.cc:
 ENDP IizVCMPLESS::
↑ VCMPUNORDSS
Compare Scalar Single-FP values Unordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORDSS:: PROC
    MOV CL,0x03
    JMP IizVCMPSS.cc:
 ENDP IizVCMPUNORDSS::
↑ VCMPNEQSS
Compare Scalar Single-FP values Not Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQSS:: PROC
    MOV CL,0x04
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNEQSS::
↑ VCMPNLTSS
Compare Scalar Single-FP values Not Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLTSS:: PROC
    MOV CL,0x05
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNLTSS::
↑ VCMPNLESS
Compare Scalar Single-FP values Not Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLESS:: PROC
    MOV CL,0x06
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNLESS::
↑ VCMPORDSS
Compare Scalar Single-FP values Ordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORDSS:: PROC
    MOV CL,0x07
    JMP IizVCMPSS.cc:
 ENDP IizVCMPORDSS::
↑ VCMPNGESS
Compare Scalar Single-FP values Not Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGESS:: PROC
    MOV CL,0x09
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNGESS::
↑ VCMPNGTSS
Compare Scalar Single-FP values Not Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGTSS:: PROC
    MOV CL,0x0A
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNGTSS::
↑ VCMPFALSESS
Compare Scalar Single-FP values False
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSESS:: PROC
    MOV CL,0x0B
    JMP IizVCMPSS.cc:
 ENDP IizVCMPFALSESS::
↑ VCMPGESS
Compare Scalar Single-FP values Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGESS:: PROC
    MOV CL,0x0D
    JMP IizVCMPSS.cc:
 ENDP IizVCMPGESS::
↑ VCMPGTSS
Compare Scalar Single-FP values Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGTSS:: PROC
    MOV CL,0x0E
    JMP IizVCMPSS.cc:
 ENDP IizVCMPGTSS::
↑ VCMPTRUESS
Compare Scalar Single-FP values True
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUESS:: PROC
    MOV CL,0x0F
    JMP IizVCMPSS.cc:
 ENDP IizVCMPTRUESS::
↑ VCMPEQ_OQSS
Compare Scalar Single-FP values Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQ_OQSS:: PROC
    MOV CL,0x00
    JMP IizVCMPSS.cc:
 ENDP IizVCMPEQ_OQSS::
↑ VCMPLT_OSSS
Compare Scalar Single-FP values Less Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLT_OSSS:: PROC
    MOV CL,0x01
    JMP IizVCMPSS.cc:
 ENDP IizVCMPLT_OSSS::
↑ VCMPLE_OSSS
Compare Scalar Single-FP values Less than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLE_OSSS:: PROC
    MOV CL,0x02
    JMP IizVCMPSS.cc:
 ENDP IizVCMPLE_OSSS::
↑ VCMPUNORD_QSS
Compare Scalar Single-FP values Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORD_QSS:: PROC
    MOV CL,0x03
    JMP IizVCMPSS.cc:
 ENDP IizVCMPUNORD_QSS::
↑ VCMPNEQ_UQSS
Compare Scalar Single-FP values Not Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQ_UQSS:: PROC
    MOV CL,0x04
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNEQ_UQSS::
↑ VCMPNLT_USSS
Compare Scalar Single-FP values Not Less Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLT_USSS:: PROC
    MOV CL,0x05
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNLT_USSS::
↑ VCMPNLE_USSS
Compare Scalar Single-FP values Not Less than or Equal,Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLE_USSS:: PROC
    MOV CL,0x06
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNLE_USSS::
↑ VCMPORD_QSS
Compare Scalar Single-FP values Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORD_QSS:: PROC
    MOV CL,0x07
    JMP IizVCMPSS.cc:
 ENDP IizVCMPORD_QSS::
↑ VCMPEQ_UQSS
Compare Scalar Single-FP values Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x08
IizVCMPEQ_UQSS:: PROC
    MOV CL,0x08
    JMP IizVCMPSS.cc:
 ENDP IizVCMPEQ_UQSS::
↑ VCMPNGE_USSS
Compare Scalar Single-FP values Not Greater than or Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGE_USSS:: PROC
    MOV CL,0x09
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNGE_USSS::
↑ VCMPNGT_USSS
Compare Scalar Single-FP values Not Greater Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGT_USSS:: PROC
    MOV CL,0x0A
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNGT_USSS::
↑ VCMPFALSE_OQSS
Compare Scalar Single-FP values False, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSE_OQSS:: PROC
    MOV CL,0x0B
    JMP IizVCMPSS.cc:
 ENDP IizVCMPFALSE_OQSS::
↑ VCMPNEQ_OQSS
Compare Scalar Single-FP values Not Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0C
IizVCMPNEQ_OQSS:: PROC
    MOV CL,0x0C
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNEQ_OQSS::
↑ VCMPGE_OSSS
Compare Scalar Single-FP values Greater than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGE_OSSS:: PROC
    MOV CL,0x0D
    JMP IizVCMPSS.cc:
 ENDP IizVCMPGE_OSSS::
↑ VCMPGT_OSSS
Compare Scalar Single-FP values Greater Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGT_OSSS:: PROC
    MOV CL,0x0E
    JMP IizVCMPSS.cc:
 ENDP IizVCMPGT_OSSS::
↑ VCMPTRUE_UQSS
Compare Scalar Single-FP values True, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUE_UQSS:: PROC
    MOV CL,0x0F
    JMP IizVCMPSS.cc:
 ENDP IizVCMPTRUE_UQSS::
↑ VCMPEQ_OSSS
Compare Scalar Single-FP values Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x10
IizVCMPEQ_OSSS:: PROC
    MOV CL,0x10
    JMP IizVCMPSS.cc:
 ENDP IizVCMPEQ_OSSS::
↑ VCMPLT_OQSS
Compare Scalar Single-FP values Less Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x11
IizVCMPLT_OQSS:: PROC
    MOV CL,0x11
    JMP IizVCMPSS.cc:
 ENDP IizVCMPLT_OQSS::
↑ VCMPLE_OQSS
Compare Scalar Single-FP values Less than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x12
IizVCMPLE_OQSS:: PROC
    MOV CL,0x12
    JMP IizVCMPSS.cc:
 ENDP IizVCMPLE_OQSS::
↑ VCMPUNORD_SSS
Compare Scalar Single-FP values Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x13
IizVCMPUNORD_SSS:: PROC
    MOV CL,0x13
    JMP IizVCMPSS.cc:
 ENDP IizVCMPUNORD_SSS::
↑ VCMPNEQ_USSS
Compare Scalar Single-FP values Not Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x14
IizVCMPNEQ_USSS:: PROC
    MOV CL,0x14
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNEQ_USSS::
↑ VCMPNLT_UQSS
Compare Scalar Single-FP values Not Less Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x15
IizVCMPNLT_UQSS:: PROC
    MOV CL,0x15
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNLT_UQSS::
↑ VCMPNLE_UQSS
Compare Scalar Single-FP values Not Less than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x16
IizVCMPNLE_UQSS:: PROC
    MOV CL,0x16
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNLE_UQSS::
↑ VCMPORD_SSS
Compare Scalar Single-FP values Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x17
IizVCMPORD_SSS:: PROC
    MOV CL,0x17
    JMP IizVCMPSS.cc:
 ENDP IizVCMPORD_SSS::
↑ VCMPEQ_USSS
Compare Scalar Single-FP values Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x18
IizVCMPEQ_USSS:: PROC
    MOV CL,0x18
    JMP IizVCMPSS.cc:
 ENDP IizVCMPEQ_USSS::
↑ VCMPNGE_UQSS
Compare Scalar Single-FP values Not Greater than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x19
IizVCMPNGE_UQSS:: PROC
    MOV CL,0x19
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNGE_UQSS::
↑ VCMPNGT_UQSS
Compare Scalar Single-FP values Not Greater Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1A
IizVCMPNGT_UQSS:: PROC
    MOV CL,0x1A
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNGT_UQSS::
↑ VCMPFALSE_OSSS
Compare Scalar Single-FP values False, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1B
IizVCMPFALSE_OSSS:: PROC
    MOV CL,0x1B
    JMP IizVCMPSS.cc:
 ENDP IizVCMPFALSE_OSSS::
↑ VCMPNEQ_OSSS
Compare Scalar Single-FP values Not Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1C
IizVCMPNEQ_OSSS:: PROC
    MOV CL,0x1C
    JMP IizVCMPSS.cc:
 ENDP IizVCMPNEQ_OSSS::
↑ VCMPGE_OQSS
Compare Scalar Single-FP values Greater than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1D
IizVCMPGE_OQSS:: PROC
    MOV CL,0x1D
    JMP IizVCMPSS.cc:
 ENDP IizVCMPGE_OQSS::
↑ VCMPGT_OQSS
Compare Scalar Single-FP values Greater Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1E
IizVCMPGT_OQSS:: PROC
    MOV CL,0x1E
    JMP IizVCMPSS.cc:
 ENDP IizVCMPGT_OQSS::
↑ VCMPTRUE_USSS
Compare Scalar Single-FP values True, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1F
IizVCMPTRUE_USSS:: PROC
    MOV CL,0x1F
    JMP IizVCMPSS.cc:
 ENDP IizVCMPTRUE_USSS::
↑ VCMPSD
Compare Scalar Double-FP Values
Intel reference
VCMPSD xmm1, xmm2, xmm3/m64, imm8 VEX.NDS.128.F2.0F.WIG C2 /r ib
VCMPSD k1 {k2}, xmm2, xmm3/m64{sae}, imm8 EVEX.NDS.LIG.F2.0F.W1 C2 /r ib
Operands
xmm/krg,xmm,xmm/mem,imm
Opcode
0xC2 /r ib
See also
VCMPSS VCMPPS VCMPPD
Tested by
t5262 
IizVCMPSD:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Operand=DH, Register=xmm
    IiEmitOpcode 0xC2
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE, Max=31
    IiDisp8EVEX T1S64
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, krg.xmm.xmm.imm, krg.xmm.mem.imm
.cc: ; This entry is called with format xmm/krg,xmm,xmm/mem (no immediate).
    IiImmCreate CL
    JMP IizVCMPSD: ; Continue as if the condition were specified by imm value. 
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.F2.0F.WIG
    RET
.krg.xmm.xmm.imm:
.krg.xmm.mem.imm:
    IiEmitPrefix EVEX.NDS.LIG.F2.0F.W1
    RET
  ENDP IizVCMPSD::
↑ VCMPEQSD
Compare Scalar Double-FP values Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQSD:: PROC
    MOV CL,0x00
    JMP IizVCMPSD.cc:
 ENDP IizVCMPEQSD::
↑ VCMPLTSD
Compare Scalar Double-FP values Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLTSD:: PROC
    MOV CL,0x01
    JMP IizVCMPSD.cc:
 ENDP IizVCMPLTSD::
↑ VCMPLESD
Compare Scalar Double-FP values Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLESD:: PROC
    MOV CL,0x02
    JMP IizVCMPSD.cc:
 ENDP IizVCMPLESD::
↑ VCMPUNORDSD
Compare Scalar Double-FP values Unordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORDSD:: PROC
    MOV CL,0x03
    JMP IizVCMPSD.cc:
 ENDP IizVCMPUNORDSD::
↑ VCMPNEQSD
Compare Scalar Double-FP values Not Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQSD:: PROC
    MOV CL,0x04
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNEQSD::
↑ VCMPNLTSD
Compare Scalar Double-FP values Not Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLTSD:: PROC
    MOV CL,0x05
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNLTSD::
↑ VCMPNLESD
Compare Scalar Double-FP values Not Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLESD:: PROC
    MOV CL,0x06
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNLESD::
↑ VCMPORDSD
Compare Scalar Double-FP values Ordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORDSD:: PROC
    MOV CL,0x07
    JMP IizVCMPSD.cc:
 ENDP IizVCMPORDSD::
↑ VCMPNGESD
Compare Scalar Double-FP values Not Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGESD:: PROC
    MOV CL,0x09
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNGESD::
↑ VCMPNGTSD
Compare Scalar Double-FP values Not Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGTSD:: PROC
    MOV CL,0x0A
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNGTSD::
↑ VCMPFALSESD
Compare Scalar Double-FP values False
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSESD:: PROC
    MOV CL,0x0B
    JMP IizVCMPSD.cc:
 ENDP IizVCMPFALSESD::
↑ VCMPGESD
Compare Scalar Double-FP values Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGESD:: PROC
    MOV CL,0x0D
    JMP IizVCMPSD.cc:
 ENDP IizVCMPGESD::
↑ VCMPGTSD
Compare Scalar Double-FP values Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGTSD:: PROC
    MOV CL,0x0E
    JMP IizVCMPSD.cc:
 ENDP IizVCMPGTSD::
↑ VCMPTRUESD
Compare Scalar Double-FP values True
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUESD:: PROC
    MOV CL,0x0F
    JMP IizVCMPSD.cc:
 ENDP IizVCMPTRUESD::
↑ VCMPEQ_OQSD
Compare Scalar Double-FP values Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQ_OQSD:: PROC
    MOV CL,0x00
    JMP IizVCMPSD.cc:
 ENDP IizVCMPEQ_OQSD::
↑ VCMPLT_OSSD
Compare Scalar Double-FP values Less Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLT_OSSD:: PROC
    MOV CL,0x01
    JMP IizVCMPSD.cc:
 ENDP IizVCMPLT_OSSD::
↑ VCMPLE_OSSD
Compare Scalar Double-FP values Less than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLE_OSSD:: PROC
    MOV CL,0x02
    JMP IizVCMPSD.cc:
 ENDP IizVCMPLE_OSSD::
↑ VCMPUNORD_QSD
Compare Scalar Double-FP values Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORD_QSD:: PROC
    MOV CL,0x03
    JMP IizVCMPSD.cc:
 ENDP IizVCMPUNORD_QSD::
↑ VCMPNEQ_UQSD
Compare Scalar Double-FP values Not Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQ_UQSD:: PROC
    MOV CL,0x04
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNEQ_UQSD::
↑ VCMPNLT_USSD
Compare Scalar Double-FP values Not Less Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLT_USSD:: PROC
    MOV CL,0x05
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNLT_USSD::
↑ VCMPNLE_USSD
Compare Scalar Double-FP values Not Less than or Equal,Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLE_USSD:: PROC
    MOV CL,0x06
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNLE_USSD::
↑ VCMPORD_QSD
Compare Scalar Double-FP values Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORD_QSD:: PROC
    MOV CL,0x07
    JMP IizVCMPSD.cc:
 ENDP IizVCMPORD_QSD::
↑ VCMPEQ_UQSD
Compare Scalar Double-FP values Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x08
IizVCMPEQ_UQSD:: PROC
    MOV CL,0x08
    JMP IizVCMPSD.cc:
 ENDP IizVCMPEQ_UQSD::
↑ VCMPNGE_USSD
Compare Scalar Double-FP values Not Greater than or Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGE_USSD:: PROC
    MOV CL,0x09
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNGE_USSD::
↑ VCMPNGT_USSD
Compare Scalar Double-FP values Not Greater Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGT_USSD:: PROC
    MOV CL,0x0A
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNGT_USSD::
↑ VCMPFALSE_OQSD
Compare Scalar Double-FP values False, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSE_OQSD:: PROC
    MOV CL,0x0B
    JMP IizVCMPSD.cc:
 ENDP IizVCMPFALSE_OQSD::
↑ VCMPNEQ_OQSD
Compare Scalar Double-FP values Not Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0C
IizVCMPNEQ_OQSD:: PROC
    MOV CL,0x0C
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNEQ_OQSD::
↑ VCMPGE_OSSD
Compare Scalar Double-FP values Greater than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGE_OSSD:: PROC
    MOV CL,0x0D
    JMP IizVCMPSD.cc:
 ENDP IizVCMPGE_OSSD::
↑ VCMPGT_OSSD
Compare Scalar Double-FP values Greater Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGT_OSSD:: PROC
    MOV CL,0x0E
    JMP IizVCMPSD.cc:
 ENDP IizVCMPGT_OSSD::
↑ VCMPTRUE_UQSD
Compare Scalar Double-FP values True, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUE_UQSD:: PROC
    MOV CL,0x0F
    JMP IizVCMPSD.cc:
 ENDP IizVCMPTRUE_UQSD::
↑ VCMPEQ_OSSD
Compare Scalar Double-FP values Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x10
IizVCMPEQ_OSSD:: PROC
    MOV CL,0x10
    JMP IizVCMPSD.cc:
 ENDP IizVCMPEQ_OSSD::
↑ VCMPLT_OQSD
Compare Scalar Double-FP values Less Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x11
IizVCMPLT_OQSD:: PROC
    MOV CL,0x11
    JMP IizVCMPSD.cc:
 ENDP IizVCMPLT_OQSD::
↑ VCMPLE_OQSD
Compare Scalar Double-FP values Less than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x12
IizVCMPLE_OQSD:: PROC
    MOV CL,0x12
    JMP IizVCMPSD.cc:
 ENDP IizVCMPLE_OQSD::
↑ VCMPUNORD_SSD
Compare Scalar Double-FP values Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x13
IizVCMPUNORD_SSD:: PROC
    MOV CL,0x13
    JMP IizVCMPSD.cc:
 ENDP IizVCMPUNORD_SSD::
↑ VCMPNEQ_USSD
Compare Scalar Double-FP values Not Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x14
IizVCMPNEQ_USSD:: PROC
    MOV CL,0x14
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNEQ_USSD::
↑ VCMPNLT_UQSD
Compare Scalar Double-FP values Not Less Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x15
IizVCMPNLT_UQSD:: PROC
    MOV CL,0x15
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNLT_UQSD::
↑ VCMPNLE_UQSD
Compare Scalar Double-FP values Not Less than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x16
IizVCMPNLE_UQSD:: PROC
    MOV CL,0x16
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNLE_UQSD::
↑ VCMPORD_SSD
Compare Scalar Double-FP values Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x17
IizVCMPORD_SSD:: PROC
    MOV CL,0x17
    JMP IizVCMPSD.cc:
 ENDP IizVCMPORD_SSD::
↑ VCMPEQ_USSD
Compare Scalar Double-FP values Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x18
IizVCMPEQ_USSD:: PROC
    MOV CL,0x18
    JMP IizVCMPSD.cc:
 ENDP IizVCMPEQ_USSD::
↑ VCMPNGE_UQSD
Compare Scalar Double-FP values Not Greater than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x19
IizVCMPNGE_UQSD:: PROC
    MOV CL,0x19
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNGE_UQSD::
↑ VCMPNGT_UQSD
Compare Scalar Double-FP values Not Greater Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1A
IizVCMPNGT_UQSD:: PROC
    MOV CL,0x1A
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNGT_UQSD::
↑ VCMPFALSE_OSSD
Compare Scalar Double-FP values False, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1B
IizVCMPFALSE_OSSD:: PROC
    MOV CL,0x1B
    JMP IizVCMPSD.cc:
 ENDP IizVCMPFALSE_OSSD::
↑ VCMPNEQ_OSSD
Compare Scalar Double-FP values Not Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1C
IizVCMPNEQ_OSSD:: PROC
    MOV CL,0x1C
    JMP IizVCMPSD.cc:
 ENDP IizVCMPNEQ_OSSD::
↑ VCMPGE_OQSD
Compare Scalar Double-FP values Greater than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1D
IizVCMPGE_OQSD:: PROC
    MOV CL,0x1D
    JMP IizVCMPSD.cc:
 ENDP IizVCMPGE_OQSD::
↑ VCMPGT_OQSD
Compare Scalar Double-FP values Greater Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1E
IizVCMPGT_OQSD:: PROC
    MOV CL,0x1E
    JMP IizVCMPSD.cc:
 ENDP IizVCMPGT_OQSD::
↑ VCMPTRUE_USSD
Compare Scalar Double-FP values True, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1F
IizVCMPTRUE_USSD:: PROC
    MOV CL,0x1F
    JMP IizVCMPSD.cc:
 ENDP IizVCMPTRUE_USSD::
↑ VCMPPS
Compare Packed Single-FP Values
Intel reference
VCMPPS xmm1, xmm2, xmm3/m128, imm8 VEX.NDS.128.0F.WIG C2 /r ib
VCMPPS ymm1, ymm2, ymm3/m256, imm8 VEX.NDS.256.0F.WIG C2 /r ib
VCMPPS k1 {k2}, xmm2, xmm3/m128/m32bcst, imm8 EVEX.NDS.128.0F.W0 C2 /r ib
VCMPPS k1 {k2}, ymm2, ymm3/m256/m32bcst, imm8 EVEX.NDS.256.0F.W0 C2 /r ib
VCMPPS k1 {k2}, zmm2, zmm3/m512/m32bcst{sae}, imm8 EVEX.NDS.512.0F.W0 C2 /r ib
VCMPPS k2 {k1}, zmm1, zmm2/mem, imm8 MVEX.NDS.512.0F.W0 C2 /r ib
Opcode
0xC2 /r imm8
See also
VCMPSS VCMPSD VCMPPD
Tested by
t5264 
IizVCMPPS:: PROC
    IiAllowModifier MASK,EH
    IiAllowBroadcasting DWORD, Operand=DH
    IiAllowSuppressing Operand=DH
    IiEmitOpcode 0xC2
    IiDisp8EVEX FV32
    IiDisp8MVEX Us32
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE, Max=31
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm,\
    krg.xmm.xmm.imm, krg.xmm.mem.imm, krg.ymm.ymm.imm, krg.ymm.mem.imm, \
    krg.zmm.zmm.imm, krg.zmm.mem.imm
.cc: ; This entry is called with format xmm/krg,xmm,xmm/mem (no immediate).
    IiImmCreate CL
    JMP IizVCMPPS: ; Continue as if the condition were specified by imm value. 
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.0F.WIG
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix VEX.NDS.256.0F.WIG
    RET
.krg.xmm.mem.imm:
.krg.xmm.xmm.imm:
    IiEmitPrefix EVEX.NDS.128.0F.W0
    RET
.krg.ymm.mem.imm:
.krg.ymm.ymm.imm:
    IiEmitPrefix EVEX.NDS.256.0F.W0
    RET
.krg.zmm.zmm.imm:
.krg.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.0F.W0, MVEX.NDS.512.0F.W0
    RET
  ENDP IizVCMPPS::
↑ VCMPEQPS
Compare Packed Single-FP values Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQPS:: PROC
    MOV CL,0x00
    JMP IizVCMPPS.cc:
 ENDP IizVCMPEQPS::
↑ VCMPLTPS
Compare Packed Single-FP values Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLTPS:: PROC
    MOV CL,0x01
    JMP IizVCMPPS.cc:
 ENDP IizVCMPLTPS::
↑ VCMPLEPS
Compare Packed Single-FP values Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLEPS:: PROC
    MOV CL,0x02
    JMP IizVCMPPS.cc:
 ENDP IizVCMPLEPS::
↑ VCMPUNORDPS
Compare Packed Single-FP values Unordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORDPS:: PROC
    MOV CL,0x03
    JMP IizVCMPPS.cc:
 ENDP IizVCMPUNORDPS::
↑ VCMPNEQPS
Compare Packed Single-FP values Not Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQPS:: PROC
    MOV CL,0x04
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNEQPS::
↑ VCMPNLTPS
Compare Packed Single-FP values Not Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLTPS:: PROC
    MOV CL,0x05
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNLTPS::
↑ VCMPNLEPS
Compare Packed Single-FP values Not Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLEPS:: PROC
    MOV CL,0x06
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNLEPS::
↑ VCMPORDPS
Compare Packed Single-FP values Ordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORDPS:: PROC
    MOV CL,0x07
    JMP IizVCMPPS.cc:
 ENDP IizVCMPORDPS::
↑ VCMPNGEPS
Compare Packed Single-FP values Not Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGEPS:: PROC
    MOV CL,0x09
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNGEPS::
↑ VCMPNGTPS
Compare Packed Single-FP values Not Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGTPS:: PROC
    MOV CL,0x0A
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNGTPS::
↑ VCMPFALSEPS
Compare Packed Single-FP values False
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSEPS:: PROC
    MOV CL,0x0B
    JMP IizVCMPPS.cc:
 ENDP IizVCMPFALSEPS::
↑ VCMPGEPS
Compare Packed Single-FP values Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGEPS:: PROC
    MOV CL,0x0D
    JMP IizVCMPPS.cc:
 ENDP IizVCMPGEPS::
↑ VCMPGTPS
Compare Packed Single-FP values Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGTPS:: PROC
    MOV CL,0x0E
    JMP IizVCMPPS.cc:
 ENDP IizVCMPGTPS::
↑ VCMPTRUEPS
Compare Packed Single-FP values True
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUEPS:: PROC
    MOV CL,0x0F
    JMP IizVCMPPS.cc:
 ENDP IizVCMPTRUEPS::
↑ VCMPEQ_OQPS
Compare Packed Single-FP values Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQ_OQPS:: PROC
    MOV CL,0x00
    JMP IizVCMPPS.cc:
 ENDP IizVCMPEQ_OQPS::
↑ VCMPLT_OSPS
Compare Packed Single-FP values Less Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLT_OSPS:: PROC
    MOV CL,0x01
    JMP IizVCMPPS.cc:
 ENDP IizVCMPLT_OSPS::
↑ VCMPLE_OSPS
Compare Packed Single-FP values Less than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLE_OSPS:: PROC
    MOV CL,0x02
    JMP IizVCMPPS.cc:
 ENDP IizVCMPLE_OSPS::
↑ VCMPUNORD_QPS
Compare Packed Single-FP values Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORD_QPS:: PROC
    MOV CL,0x03
    JMP IizVCMPPS.cc:
 ENDP IizVCMPUNORD_QPS::
↑ VCMPNEQ_UQPS
Compare Packed Single-FP values Not Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQ_UQPS:: PROC
    MOV CL,0x04
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNEQ_UQPS::
↑ VCMPNLT_USPS
Compare Packed Single-FP values Not Less Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLT_USPS:: PROC
    MOV CL,0x05
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNLT_USPS::
↑ VCMPNLE_USPS
Compare Packed Single-FP values Not Less than or Equal,Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLE_USPS:: PROC
    MOV CL,0x06
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNLE_USPS::
↑ VCMPORD_QPS
Compare Packed Single-FP values Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORD_QPS:: PROC
    MOV CL,0x07
    JMP IizVCMPPS.cc:
 ENDP IizVCMPORD_QPS::
↑ VCMPEQ_UQPS
Compare Packed Single-FP values Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x08
IizVCMPEQ_UQPS:: PROC
    MOV CL,0x08
    JMP IizVCMPPS.cc:
 ENDP IizVCMPEQ_UQPS::
↑ VCMPNGE_USPS
Compare Packed Single-FP values Not Greater than or Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGE_USPS:: PROC
    MOV CL,0x09
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNGE_USPS::
↑ VCMPNGT_USPS
Compare Packed Single-FP values Not Greater Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGT_USPS:: PROC
    MOV CL,0x0A
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNGT_USPS::
↑ VCMPFALSE_OQPS
Compare Packed Single-FP values False, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSE_OQPS:: PROC
    MOV CL,0x0B
    JMP IizVCMPPS.cc:
 ENDP IizVCMPFALSE_OQPS::
↑ VCMPNEQ_OQPS
Compare Packed Single-FP values Not Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0C
IizVCMPNEQ_OQPS:: PROC
    MOV CL,0x0C
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNEQ_OQPS::
↑ VCMPGE_OSPS
Compare Packed Single-FP values Greater than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGE_OSPS:: PROC
    MOV CL,0x0D
    JMP IizVCMPPS.cc:
 ENDP IizVCMPGE_OSPS::
↑ VCMPGT_OSPS
Compare Packed Single-FP values Greater Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGT_OSPS:: PROC
    MOV CL,0x0E
    JMP IizVCMPPS.cc:
 ENDP IizVCMPGT_OSPS::
↑ VCMPTRUE_UQPS
Compare Packed Single-FP values True, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUE_UQPS:: PROC
    MOV CL,0x0F
    JMP IizVCMPPS.cc:
 ENDP IizVCMPTRUE_UQPS::
↑ VCMPEQ_OSPS
Compare Packed Single-FP values Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x10
IizVCMPEQ_OSPS:: PROC
    MOV CL,0x10
    JMP IizVCMPPS.cc:
 ENDP IizVCMPEQ_OSPS::
↑ VCMPLT_OQPS
Compare Packed Single-FP values Less Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x11
IizVCMPLT_OQPS:: PROC
    MOV CL,0x11
    JMP IizVCMPPS.cc:
 ENDP IizVCMPLT_OQPS::
↑ VCMPLE_OQPS
Compare Packed Single-FP values Less than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x12
IizVCMPLE_OQPS:: PROC
    MOV CL,0x12
    JMP IizVCMPPS.cc:
 ENDP IizVCMPLE_OQPS::
↑ VCMPUNORD_SPS
Compare Packed Single-FP values Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x13
IizVCMPUNORD_SPS:: PROC
    MOV CL,0x13
    JMP IizVCMPPS.cc:
 ENDP IizVCMPUNORD_SPS::
↑ VCMPNEQ_USPS
Compare Packed Single-FP values Not Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x14
IizVCMPNEQ_USPS:: PROC
    MOV CL,0x14
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNEQ_USPS::
↑ VCMPNLT_UQPS
Compare Packed Single-FP values Not Less Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x15
IizVCMPNLT_UQPS:: PROC
    MOV CL,0x15
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNLT_UQPS::
↑ VCMPNLE_UQPS
Compare Packed Single-FP values Not Less than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x16
IizVCMPNLE_UQPS:: PROC
    MOV CL,0x16
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNLE_UQPS::
↑ VCMPORD_SPS
Compare Packed Single-FP values Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x17
IizVCMPORD_SPS:: PROC
    MOV CL,0x17
    JMP IizVCMPPS.cc:
 ENDP IizVCMPORD_SPS::
↑ VCMPEQ_USPS
Compare Packed Single-FP values Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x18
IizVCMPEQ_USPS:: PROC
    MOV CL,0x18
    JMP IizVCMPPS.cc:
 ENDP IizVCMPEQ_USPS::
↑ VCMPNGE_UQPS
Compare Packed Single-FP values Not Greater than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x19
IizVCMPNGE_UQPS:: PROC
    MOV CL,0x19
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNGE_UQPS::
↑ VCMPNGT_UQPS
Compare Packed Single-FP values Not Greater Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1A
IizVCMPNGT_UQPS:: PROC
    MOV CL,0x1A
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNGT_UQPS::
↑ VCMPFALSE_OSPS
Compare Packed Single-FP values False, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1B
IizVCMPFALSE_OSPS:: PROC
    MOV CL,0x1B
    JMP IizVCMPPS.cc:
 ENDP IizVCMPFALSE_OSPS::
↑ VCMPNEQ_OSPS
Compare Packed Single-FP values Not Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1C
IizVCMPNEQ_OSPS:: PROC
    MOV CL,0x1C
    JMP IizVCMPPS.cc:
 ENDP IizVCMPNEQ_OSPS::
↑ VCMPGE_OQPS
Compare Packed Single-FP values Greater than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1D
IizVCMPGE_OQPS:: PROC
    MOV CL,0x1D
    JMP IizVCMPPS.cc:
 ENDP IizVCMPGE_OQPS::
↑ VCMPGT_OQPS
Compare Packed Single-FP values Greater Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1E
IizVCMPGT_OQPS:: PROC
    MOV CL,0x1E
    JMP IizVCMPPS.cc:
 ENDP IizVCMPGT_OQPS::
↑ VCMPTRUE_USPS
Compare Packed Single-FP values True, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1F
IizVCMPTRUE_USPS:: PROC
    MOV CL,0x1F
    JMP IizVCMPPS.cc:
 ENDP IizVCMPTRUE_USPS::
↑ VCMPPD
Compare Packed Double-FP Values
Intel reference
VCMPPD xmm1, xmm2, xmm3/m128, imm8 VEX.NDS.128.66.0F.WIG C2 /r ib
VCMPPD ymm1, ymm2, ymm3/m256, imm8 VEX.NDS.256.66.0F.WIG C2 /r ib
VCMPPD k1 {k2}, xmm2, xmm3/m128/m64bcst, imm8 EVEX.NDS.128.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, ymm2, ymm3/m256/m64bcst, imm8 EVEX.NDS.256.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, zmm2, zmm3/m512/m64bcst{sae}, imm8 EVEX.NDS.512.66.0F.W1 C2 /r ib
VCMPPD k2 {k1}, zmm1, zmm2/mem, imm8 MVEX.NDS.512.66.0F.W1 C2 /r ib
Opcode
0xC2 /r imm8
See also
VCMPSS VCMPSD VCMPPS
Tested by
t5266 
IizVCMPPD:: PROC
    IiAllowModifier MASK,EH
    IiAllowBroadcasting QWORD, Operand=DH
    IiAllowSuppressing Operand=DH
    IiEmitOpcode 0xC2
    IiDisp8EVEX FV64
    IiDisp8MVEX Ub64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE, Max=31
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm,\
    krg.xmm.xmm.imm, krg.xmm.mem.imm, krg.ymm.ymm.imm, krg.ymm.mem.imm, \
    krg.zmm.zmm.imm, krg.zmm.mem.imm
.cc: ; This entry is called with format xmm/krg,xmm,xmm/mem (no immediate).
    IiImmCreate CL
    JMP IizVCMPPD: ; Continue as if the condition were specified by imm value. 
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG
    RET
.krg.xmm.mem.imm:
.krg.xmm.xmm.imm:
    IiEmitPrefix EVEX.NDS.128.66.0F.W1
    RET
.krg.ymm.mem.imm:
.krg.ymm.ymm.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F.W1
    RET
.krg.zmm.zmm.imm:
.krg.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F.W1, MVEX.NDS.512.66.0F.W1
    RET
  ENDP IizVCMPPD::
↑ VCMPEQPD
Compare Packed Double-FP values Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQPD:: PROC
    MOV CL,0x00
    JMP IizVCMPPD.cc:
 ENDP IizVCMPEQPD::
↑ VCMPLTPD
Compare Packed Double-FP values Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLTPD:: PROC
    MOV CL,0x01
    JMP IizVCMPPD.cc:
 ENDP IizVCMPLTPD::
↑ VCMPLEPD
Compare Packed Double-FP values Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLEPD:: PROC
    MOV CL,0x02
    JMP IizVCMPPD.cc:
 ENDP IizVCMPLEPD::
↑ VCMPUNORDPD
Compare Packed Double-FP values Unordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORDPD:: PROC
    MOV CL,0x03
    JMP IizVCMPPD.cc:
 ENDP IizVCMPUNORDPD::
↑ VCMPNEQPD
Compare Packed Double-FP values Not Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQPD:: PROC
    MOV CL,0x04
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNEQPD::
↑ VCMPNLTPD
Compare Packed Double-FP values Not Less Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLTPD:: PROC
    MOV CL,0x05
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNLTPD::
↑ VCMPNLEPD
Compare Packed Double-FP values Not Less than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLEPD:: PROC
    MOV CL,0x06
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNLEPD::
↑ VCMPORDPD
Compare Packed Double-FP values Ordered
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORDPD:: PROC
    MOV CL,0x07
    JMP IizVCMPPD.cc:
 ENDP IizVCMPORDPD::
↑ VCMPNGEPD
Compare Packed Double-FP values Not Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGEPD:: PROC
    MOV CL,0x09
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNGEPD::
↑ VCMPNGTPD
Compare Packed Double-FP values Not Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGTPD:: PROC
    MOV CL,0x0A
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNGTPD::
↑ VCMPFALSEPD
Compare Packed Double-FP values False
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSEPD:: PROC
    MOV CL,0x0B
    JMP IizVCMPPD.cc:
 ENDP IizVCMPFALSEPD::
↑ VCMPGEPD
Compare Packed Double-FP values Greater than or Equal
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGEPD:: PROC
    MOV CL,0x0D
    JMP IizVCMPPD.cc:
 ENDP IizVCMPGEPD::
↑ VCMPGTPD
Compare Packed Double-FP values Greater Than
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGTPD:: PROC
    MOV CL,0x0E
    JMP IizVCMPPD.cc:
 ENDP IizVCMPGTPD::
↑ VCMPTRUEPD
Compare Packed Double-FP values True
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUEPD:: PROC
    MOV CL,0x0F
    JMP IizVCMPPD.cc:
 ENDP IizVCMPTRUEPD::
↑ VCMPEQ_OQPD
Compare Packed Double-FP values Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x00
IizVCMPEQ_OQPD:: PROC
    MOV CL,0x00
    JMP IizVCMPPD.cc:
 ENDP IizVCMPEQ_OQPD::
↑ VCMPLT_OSPD
Compare Packed Double-FP values Less Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x01
IizVCMPLT_OSPD:: PROC
    MOV CL,0x01
    JMP IizVCMPPD.cc:
 ENDP IizVCMPLT_OSPD::
↑ VCMPLE_OSPD
Compare Packed Double-FP values Less than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x02
IizVCMPLE_OSPD:: PROC
    MOV CL,0x02
    JMP IizVCMPPD.cc:
 ENDP IizVCMPLE_OSPD::
↑ VCMPUNORD_QPD
Compare Packed Double-FP values Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x03
IizVCMPUNORD_QPD:: PROC
    MOV CL,0x03
    JMP IizVCMPPD.cc:
 ENDP IizVCMPUNORD_QPD::
↑ VCMPNEQ_UQPD
Compare Packed Double-FP values Not Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x04
IizVCMPNEQ_UQPD:: PROC
    MOV CL,0x04
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNEQ_UQPD::
↑ VCMPNLT_USPD
Compare Packed Double-FP values Not Less Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x05
IizVCMPNLT_USPD:: PROC
    MOV CL,0x05
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNLT_USPD::
↑ VCMPNLE_USPD
Compare Packed Double-FP values Not Less than or Equal,Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x06
IizVCMPNLE_USPD:: PROC
    MOV CL,0x06
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNLE_USPD::
↑ VCMPORD_QPD
Compare Packed Double-FP values Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x07
IizVCMPORD_QPD:: PROC
    MOV CL,0x07
    JMP IizVCMPPD.cc:
 ENDP IizVCMPORD_QPD::
↑ VCMPEQ_UQPD
Compare Packed Double-FP values Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x08
IizVCMPEQ_UQPD:: PROC
    MOV CL,0x08
    JMP IizVCMPPD.cc:
 ENDP IizVCMPEQ_UQPD::
↑ VCMPNGE_USPD
Compare Packed Double-FP values Not Greater than or Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x09
IizVCMPNGE_USPD:: PROC
    MOV CL,0x09
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNGE_USPD::
↑ VCMPNGT_USPD
Compare Packed Double-FP values Not Greater Than, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0A
IizVCMPNGT_USPD:: PROC
    MOV CL,0x0A
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNGT_USPD::
↑ VCMPFALSE_OQPD
Compare Packed Double-FP values False, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0B
IizVCMPFALSE_OQPD:: PROC
    MOV CL,0x0B
    JMP IizVCMPPD.cc:
 ENDP IizVCMPFALSE_OQPD::
↑ VCMPNEQ_OQPD
Compare Packed Double-FP values Not Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0C
IizVCMPNEQ_OQPD:: PROC
    MOV CL,0x0C
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNEQ_OQPD::
↑ VCMPGE_OSPD
Compare Packed Double-FP values Greater than or Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0D
IizVCMPGE_OSPD:: PROC
    MOV CL,0x0D
    JMP IizVCMPPD.cc:
 ENDP IizVCMPGE_OSPD::
↑ VCMPGT_OSPD
Compare Packed Double-FP values Greater Than, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0E
IizVCMPGT_OSPD:: PROC
    MOV CL,0x0E
    JMP IizVCMPPD.cc:
 ENDP IizVCMPGT_OSPD::
↑ VCMPTRUE_UQPD
Compare Packed Double-FP values True, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x0F
IizVCMPTRUE_UQPD:: PROC
    MOV CL,0x0F
    JMP IizVCMPPD.cc:
 ENDP IizVCMPTRUE_UQPD::
↑ VCMPEQ_OSPD
Compare Packed Double-FP values Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x10
IizVCMPEQ_OSPD:: PROC
    MOV CL,0x10
    JMP IizVCMPPD.cc:
 ENDP IizVCMPEQ_OSPD::
↑ VCMPLT_OQPD
Compare Packed Double-FP values Less Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x11
IizVCMPLT_OQPD:: PROC
    MOV CL,0x11
    JMP IizVCMPPD.cc:
 ENDP IizVCMPLT_OQPD::
↑ VCMPLE_OQPD
Compare Packed Double-FP values Less than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x12
IizVCMPLE_OQPD:: PROC
    MOV CL,0x12
    JMP IizVCMPPD.cc:
 ENDP IizVCMPLE_OQPD::
↑ VCMPUNORD_SPD
Compare Packed Double-FP values Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x13
IizVCMPUNORD_SPD:: PROC
    MOV CL,0x13
    JMP IizVCMPPD.cc:
 ENDP IizVCMPUNORD_SPD::
↑ VCMPNEQ_USPD
Compare Packed Double-FP values Not Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x14
IizVCMPNEQ_USPD:: PROC
    MOV CL,0x14
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNEQ_USPD::
↑ VCMPNLT_UQPD
Compare Packed Double-FP values Not Less Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x15
IizVCMPNLT_UQPD:: PROC
    MOV CL,0x15
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNLT_UQPD::
↑ VCMPNLE_UQPD
Compare Packed Double-FP values Not Less than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x16
IizVCMPNLE_UQPD:: PROC
    MOV CL,0x16
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNLE_UQPD::
↑ VCMPORD_SPD
Compare Packed Double-FP values Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x17
IizVCMPORD_SPD:: PROC
    MOV CL,0x17
    JMP IizVCMPPD.cc:
 ENDP IizVCMPORD_SPD::
↑ VCMPEQ_USPD
Compare Packed Double-FP values Equal, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x18
IizVCMPEQ_USPD:: PROC
    MOV CL,0x18
    JMP IizVCMPPD.cc:
 ENDP IizVCMPEQ_USPD::
↑ VCMPNGE_UQPD
Compare Packed Double-FP values Not Greater than or Equal, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x19
IizVCMPNGE_UQPD:: PROC
    MOV CL,0x19
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNGE_UQPD::
↑ VCMPNGT_UQPD
Compare Packed Double-FP values Not Greater Than, Unordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1A
IizVCMPNGT_UQPD:: PROC
    MOV CL,0x1A
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNGT_UQPD::
↑ VCMPFALSE_OSPD
Compare Packed Double-FP values False, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1B
IizVCMPFALSE_OSPD:: PROC
    MOV CL,0x1B
    JMP IizVCMPPD.cc:
 ENDP IizVCMPFALSE_OSPD::
↑ VCMPNEQ_OSPD
Compare Packed Double-FP values Not Equal, Ordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1C
IizVCMPNEQ_OSPD:: PROC
    MOV CL,0x1C
    JMP IizVCMPPD.cc:
 ENDP IizVCMPNEQ_OSPD::
↑ VCMPGE_OQPD
Compare Packed Double-FP values Greater than or Equal, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1D
IizVCMPGE_OQPD:: PROC
    MOV CL,0x1D
    JMP IizVCMPPD.cc:
 ENDP IizVCMPGE_OQPD::
↑ VCMPGT_OQPD
Compare Packed Double-FP values Greater Than, Ordered, Quiet
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1E
IizVCMPGT_OQPD:: PROC
    MOV CL,0x1E
    JMP IizVCMPPD.cc:
 ENDP IizVCMPGT_OQPD::
↑ VCMPTRUE_USPD
Compare Packed Double-FP values True, Unordered, Signaling
Operands
xmm/krg, xmm, xmm/mem
Opcode
0xC2 /r 0x1F
IizVCMPTRUE_USPD:: PROC
    MOV CL,0x1F
    JMP IizVCMPPD.cc:
 ENDP IizVCMPTRUE_USPD::
↑ VUCOMISS
Unordered Compare Scalar Single-FP Values and Set EFLAGS
Intel reference
VUCOMISS xmm1, xmm2/m32 VEX.128.0F.WIG 2E /r
VUCOMISS xmm1, xmm2/m32{sae} EVEX.LIG.0F.W0 2E /r
Category
sse1,simdfp,compar
Operands
Vss,Wss
Opcode
0x0F2E /r
Flags
modified:....Z.PC, defined:....Z.PC
CPU
P3+
Tested by
t5268 
IizVUCOMISS:: PROC
    IiEmitOpcode 0x2E
.op:IiAllowSuppressing Register=xmm
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.0F.WIG, EVEX.LIG.0F.W0
    RET
  ENDP IizVUCOMISS::
↑ VCOMISS
Compare Scalar Ordered Single-FP Values and Set EFLAGS
Intel reference
VCOMISS xmm1, xmm2/m32 VEX.128.0F.WIG 2F /r
VCOMISS xmm1, xmm2/m32{sae} EVEX.LIG.0F.W0 2F /r
Category
sse1,simdfp,compar
Operands
Vss,Wss
Opcode
0x0F2F /r
Flags
modified:....Z.PC, defined:....Z.PC
CPU
P3+
Tested by
t5268 
IizVCOMISS:: PROC
    IiEmitOpcode 0x2F
    JMP IizVUCOMISS.op:
  ENDP IizVCOMISS::
↑ VUCOMISD
Unordered Compare Scalar Double-FP Values and Set EFLAGS
Intel reference
VUCOMISD xmm1, xmm2/m64 VEX.128.66.0F.WIG 2E /r
VUCOMISD xmm1, xmm2/m64{sae} EVEX.LIG.66.0F.W1 2E /r
Category
sse2,pcksclr,compar
Operands
Vsd,Wsd
Opcode
0x660F2E /r
Flags
modified:....Z.PC, defined:....Z.PC
CPU
P4+
Tested by
t5268 
IizVUCOMISD:: PROC
    IiEmitOpcode 0x2E
.op:IiAllowSuppressing Register=xmm
    IiEncoding DATA=QWORD
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.LIG.66.0F.W1
    RET
  ENDP IizVUCOMISD::
↑ VCOMISD
Compare Scalar Ordered Double-FP Values and Set EFLAGS
Intel reference
VCOMISD xmm1, xmm2/m64 VEX.128.66.0F.WIG 2F /r
VCOMISD xmm1, xmm2/m64{sae} EVEX.LIG.66.0F.W1 2F /r
Category
sse2,pcksclr,compar
Operands
Vsd,Wsd
Opcode
0x660F2F /r
Flags
modified:....Z.PC, defined:....Z.PC
CPU
P4+
Tested by
t5268 
IizVCOMISD:: PROC
    IiEmitOpcode 0x2F
    JMP IizVUCOMISD.op:
  ENDP IizVCOMISD::
↑ VCOMPRESSPS
Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory
Intel reference
VCOMPRESSPS xmm1/m128 {k1}{z}, xmm2 EVEX.128.66.0F38.W0 8A /r
VCOMPRESSPS ymm1/m256 {k1}{z}, ymm2 EVEX.256.66.0F38.W0 8A /r
VCOMPRESSPS zmm1/m512 {k1}{z}, zmm2 EVEX.512.66.0F38.W0 8A /r
Opcode
0x8A
Tested by
t5270 
IizVCOMPRESSPS:: PROC
    IiEmitOpcode 0x8A
.op:IiAllowModifier MASK
    IiDisp8EVEX T1S32
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat  xmm.xmm, mem.xmm, ymm.ymm, mem.ymm, zmm.zmm, mem.zmm
.mem.xmm:
.xmm.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
.mem.ymm:
.ymm.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.mem.zmm:
.zmm.zmm:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
  ENDP IizVCOMPRESSPS::
↑ VPCOMPRESSD
Store Sparse Packed Doubleword Integer Values into Dense Memory/Register
Intel reference
VPCOMPRESSD xmm1/m128 {k1}{z}, xmm2 EVEX.128.66.0F38.W0 8B /r
VPCOMPRESSD ymm1/m256 {k1}{z}, ymm2 EVEX.256.66.0F38.W0 8B /r
VPCOMPRESSD zmm1/m512 {k1}{z}, zmm2EVEX.512.66.0F38.W0 8B /r
Opcode
0x8B
Tested by
t5270 
IizVPCOMPRESSD:: PROC
    IiEmitOpcode 0x8B
    JMP IizVCOMPRESSPS.op:
  ENDP IizVPCOMPRESSD::
↑ VCOMPRESSPD
Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory
Intel reference
VCOMPRESSPD xmm1/m128 {k1}{z}, xmm2 EVEX.128.66.0F38.W1 8A /r
VCOMPRESSPD ymm1/m256 {k1}{z}, ymm2 EVEX.256.66.0F38.W1 8A /r
VCOMPRESSPD zmm1/m512 {k1}{z}, zmm2 EVEX.512.66.0F38.W1 8A /r
Opcode
0x8A
Tested by
t5270 
IizVCOMPRESSPD:: PROC
    IiEmitOpcode 0x8A
.op:IiAllowModifier MASK
    IiDisp8EVEX T1S64
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat  xmm.xmm, mem.xmm, ymm.ymm, mem.ymm, zmm.zmm, mem.zmm
.mem.xmm:
.xmm.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W1
    RET
.mem.ymm:
.ymm.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.mem.zmm:
.zmm.zmm:
    IiEmitPrefix EVEX.512.66.0F38.W1
    RET
  ENDP IizVCOMPRESSPD::
↑ VPCOMPRESSQ
Store Sparse Packed Quadword Integer Values into Dense Memory/Register
Intel reference
VPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2 EVEX.128.66.0F38.W1 8B /r
VPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2 EVEX.256.66.0F38.W1 8B /r
VPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2 EVEX.512.66.0F38.W1 8B /r
Opcode
0x8B
Tested by
t5270 
IizVPCOMPRESSQ:: PROC
    IiEmitOpcode 0x8B
    JMP IizVCOMPRESSPD.op:
  ENDP IizVPCOMPRESSQ::
↑ VMPSADBW
Compute Multiple Packed Sums of Absolute Difference
Intel reference
VMPSADBW xmm1, xmm2, xmm3/m128, imm8 VEX.NDS.128.66.0F3A.WIG 42 /r ib
VMPSADBW ymm1, ymm2, ymm3/m256, imm8 VEX.NDS.256.66.0F3A.WIG 42 /r ib
Category
sse41,simdint,arith
Operands
Vdq,Wdq,Ib
Opcode
0x660F3A42 /r
CPU
C2++
Documented
D43
Tested by
t5280 
IizVMPSADBW:: PROC
    IiEmitOpcode 0x42
    IiOpEn RVM 
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.66.0F3A.WIG
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix VEX.NDS.256.66.0F3A.WIG
    RET
  ENDP IizVMPSADBW::
↑ VDBPSADBW
Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
Intel reference
VDBPSADBW xmm1 {k1}{z}, xmm2, xmm3/m128, imm8 EVEX.NDS.128.66.0F3A.W0 42 /r ib
VDBPSADBW ymm1 {k1}{z}, ymm2, ymm3/m256, imm8 EVEX.NDS.256.66.0F3A.W0 42 /r ib
VDBPSADBW zmm1 {k1}{z}, zmm2, zmm3/m512, imm8 EVEX.NDS.512.66.0F3A.W0 42 /r ib
Opcode
0x42
Tested by
t5280 
IizVDBPSADBW:: PROC
    IiAllowModifier MASK
    IiEmitOpcode 0x42
    IiDisp8EVEX FVM
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix EVEX.NDS.128.66.0F3A.W0
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W0
    RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W0
    RET
  ENDP IizVDBPSADBW::
↑ VDPPS
Dot Product of Packed Single-FP Values
Intel reference
VDPPS xmm1,xmm2, xmm3/m128, imm8 VEX.NDS.128.66.0F3A.WIG 40 /r ib
VDPPS ymm1, ymm2, ymm3/m256, imm8 VEX.NDS.256.66.0F3A.WIG 40 /r ib
Category
sse41,simdfp,arith
Operands
Vps,Wps
Opcode
0x660F3A40 /r
CPU
C2++
Documented
D43
Tested by
t5280 
IizVDPPS:: PROC
    IiEmitOpcode 0x40
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.66.0F3A.WIG
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix VEX.NDS.256.66.0F3A.WIG
    RET
  ENDP IizVDPPS::
↑ VDPPD
Dot Product of Packed Double-FP Values
Intel reference
VDPPD xmm1,xmm2, xmm3/m128, imm8 VEX.NDS.128.66.0F3A.WIG 41 /r ib
Category
sse41,simdfp,arith
Operands
Vpd,Wpd
Opcode
0x660F3A41 /r
CPU
C2++
Documented
D43
Tested by
t5280 
IizVDPPD:: PROC
    IiEmitOpcode 0x41
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.128.66.0F3A.WIG
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVDPPD::
↑ VEXPANDPS
Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory
Intel reference
VEXPANDPS xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F38.W0 88 /r
VEXPANDPS ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F38.W0 88 /r
VEXPANDPS zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F38.W0 88 /r
Opcode
0x88
Tested by
t5275 
IizVEXPANDPS:: PROC
    IiEmitOpcode 0x88
.op:IiAllowModifier MASK
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
  ENDP IizVEXPANDPS::
↑ VPEXPANDD
Load Sparse Packed Doubleword Integer Values from Dense Memory / Register
Intel reference
VPEXPANDD xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F38.W0 89 /r
VPEXPANDD ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F38.W0 89 /r
VPEXPANDD zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F38.W0 89 /r
Opcode
0x89
Tested by
t5275 
IizVPEXPANDD:: PROC
    IiEmitOpcode 0x89
    JMP IizVEXPANDPS.op:
  ENDP IizVPEXPANDD::
↑ VEXPANDPD
Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory
Intel reference
VEXPANDPD xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F38.W1 88 /r
VEXPANDPD ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F38.W1 88 /r
VEXPANDPD zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F38.W1 88 /r
Opcode
0x88
Tested by
t5275 
IizVEXPANDPD:: PROC
    IiEmitOpcode 0x88
.op:IiAllowModifier MASK
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W1
    RET
  ENDP IizVEXPANDPD::
↑ VPEXPANDQ
Load Sparse Packed Quadword Integer Values from Dense Memory / Register
Intel reference
VPEXPANDQ xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F38.W1 89 /r
VPEXPANDQ ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F38.W1 89 /r
VPEXPANDQ zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F38.W1 89 /r
Opcode
0x89
Tested by
t5275 
IizVPEXPANDQ:: PROC
    IiEmitOpcode 0x89
    JMP IizVEXPANDPD.op:
  ENDP IizVPEXPANDQ::
↑ VEXTRACTF32X4
Extract Packed Floating-Point Values
Intel reference
VEXTRACTF32X4 xmm1/m128 {k1}{z}, ymm2, imm8 EVEX.256.66.0F3A.W0 19 /r ib
VEXTRACTF32X4 xmm1/m128 {k1}{z}, zmm2, imm8 EVEX.512.66.0F3A.W0 19 /r ib
Opcode
0x19
Tested by
t5290 
IizVEXTRACTF32X4:: PROC
    IiEmitOpcode 0x19
.op:IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiDisp8EVEX T2F64
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3,BYTE
    IiDispatchFormat  xmm.ymm.imm, mem.ymm.imm, xmm.zmm.imm, mem.zmm.imm
.xmm.ymm.imm:
.mem.ymm.imm:
    IiEmitPrefix EVEX.256.66.0F3A.W0
    RET
.xmm.zmm.imm:
.mem.zmm.imm:
    IiEmitPrefix EVEX.512.66.0F3A.W0
    RET
  ENDP IizVEXTRACTF32X4::
↑ VEXTRACTI32X4
Extract packed Integer Values
Intel reference
VEXTRACTI32X4 xmm1/m128 {k1}{z}, ymm2, imm8 EVEX.256.66.0F3A.W0 39 /r ib
VEXTRACTI32X4 xmm1/m128 {k1}{z}, zmm2, imm8EVEX.512.66.0F3A.W0 39 /r ib
Opcode
0x39
Tested by
t5292 
IizVEXTRACTI32X4:: PROC
    IiEmitOpcode 0x39
    JMP IizVEXTRACTF32X4.op:
  ENDP IizVEXTRACTI32X4::
↑ VEXTRACTF32X8
Extract Packed Floating-Point Values Opcode/ Op / 64/32
Intel reference
VEXTRACTF32X8 ymm1/m256 {k1}{z}, zmm2, imm8 EVEX.512.66.0F3A.W0 1B /r ib
Opcode
0x1B
Tested by
t5290 
IizVEXTRACTF32X8:: PROC
    IiEmitOpcode 0x1B
.op:IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiDisp8EVEX T4F64
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix EVEX.512.66.0F3A.W0
    IiDispatchFormat  ymm.zmm.imm, mem.zmm.imm
.ymm.zmm.imm:
.mem.zmm.imm:
    RET
  ENDP IizVEXTRACTF32X8::
↑ VEXTRACTI32X8
Extract packed Integer Values
Intel reference
VEXTRACTI32X8 ymm1/m256 {k1}{z}, zmm2, imm8 EVEX.512.66.0F3A.W0 3B /r ib
Opcode
0x39
Tested by
t5292 
IizVEXTRACTI32X8:: PROC
    IiEmitOpcode 0x3B
    JMP IizVEXTRACTF32X8.op:
  ENDP IizVEXTRACTI32X8::
↑ VEXTRACTF64X2
Extract Packed Floating-Point Values
Intel reference
VEXTRACTF64X2 xmm1/m128 {k1}{z}, ymm2, imm8 EVEX.256.66.0F3A.W1 19 /r ib
VEXTRACTF64X2 xmm1/m128 {k1}{z}, zmm2, imm8 EVEX.512.66.0F3A.W1 19 /r ib
Opcode
0x19
Tested by
t5290 
IizVEXTRACTF64X2:: PROC
    IiEmitOpcode 0x19
.op:IiAllowModifier MASK
    IiEncoding DATA=QWORD
    IiDisp8EVEX T2F64
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat  xmm.ymm.imm, mem.ymm.imm, xmm.zmm.imm, mem.zmm.imm
.xmm.ymm.imm:
.mem.ymm.imm:
    IiEmitPrefix EVEX.256.66.0F3A.W1
    RET
.xmm.zmm.imm:
.mem.zmm.imm:
    IiEmitPrefix EVEX.512.66.0F3A.W1
    RET
  ENDP IizVEXTRACTF64X2::
↑ VEXTRACTI64X2
Extract packed Integer Values
Intel reference
VEXTRACTI64X2 xmm1/m128 {k1}{z}, ymm2, imm8 EVEX.256.66.0F3A.W1 39 /r ib
VEXTRACTI64X2 xmm1/m128 {k1}{z}, zmm2, imm8 EVEX.512.66.0F3A.W1 39 /r ib
Opcode
0x39
Tested by
t5292 
IizVEXTRACTI64X2:: PROC
    IiEmitOpcode 0x39
    JMP IizVEXTRACTF64X2.op:
  ENDP IizVEXTRACTI64X2::
↑ VEXTRACTF64X4
Extract Packed Floating-Point Values
Intel reference
VEXTRACTF64X4 ymm1/m256 {k1}{z}, zmm2, imm8 EVEX.512.66.0F3A.W1 1B /r ib
Opcode
0x1B
Tested by
t5290 
IizVEXTRACTF64X4:: PROC
    IiEmitOpcode 0x1B
.op:IiAllowModifier MASK
    IiEncoding DATA=QWORD
    IiDisp8EVEX T4F64
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix EVEX.512.66.0F3A.W1
    IiDispatchFormat  ymm.zmm.imm, mem.zmm.imm
.ymm.zmm.imm:
.mem.zmm.imm:
    RET
  ENDP IizVEXTRACTF64X4::
↑ VEXTRACTI64X4
Extract packed Integer Values
Intel reference
VEXTRACTI64X4 ymm1/m256 {k1}{z}, zmm2, imm8 EVEX.512.66.0F3A.W1 3B /r ib
Opcode
0x3B
Tested by
t5292 
IizVEXTRACTI64X4:: PROC
    IiEmitOpcode 0x3B
    JMP IizVEXTRACTF64X4.op:
  ENDP IizVEXTRACTI64X4::
↑ VEXTRACTF128
Extract Packed Floating-Point Values
Description
VEXTRACTF128
Intel reference
VEXTRACTF128 xmm1/m128, ymm2, imm8 VEX.256.66.0F3A.W0 19 /r ib
Opcode
0x19
Tested by
t5290 
IizVEXTRACTF128:: PROC
    IiEmitOpcode 0x19
.op:IiEncoding DATA=OWORD
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix VEX.256.66.0F3A.W0
    IiDispatchFormat  xmm.ymm.imm, mem.ymm.imm
.xmm.ymm.imm:
.mem.ymm.imm:
    RET
  ENDP IizVEXTRACTF128::
↑ VEXTRACTI128
Extract packed Integer Values
Description
VEXTRACTI128
Intel reference
VEXTRACTI128 xmm1/m128, ymm2, imm8 VEX.256.66.0F3A.W0 39 /r ib
Opcode
0x39
Tested by
t5292 
IizVEXTRACTI128:: PROC
    IiEmitOpcode 0x39
    JMP IizVEXTRACTF128.op:
  ENDP IizVEXTRACTI128::
↑ VEXTRACTPS
Extract Packed Single-FP Value
Intel reference
VEXTRACTPS reg/m32, xmm1, imm8 VEX.128.66.0F3A.WIG 17 /r ib
VEXTRACTPS reg/m32, xmm1, imm8 EVEX.128.66.0F3A.WIG 17 /r ib
Category
sse41,simdfp,datamov
Operands
Ed,Vdq,Ib
Opcode
0x660F3A17 /r
CPU
C2++
Documented
D43
Tested by
t5290 
IizVEXTRACTPS:: PROC
    IiRequire SSE4.1
    IiEmitOpcode 0x17
    IiDisp8EVEX T1S32
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix VEX.128.66.0F3A.WIG, EVEX.128.66.0F3A.WIG
    IiDispatchFormat  r64.xmm.imm, r32.xmm.imm, mem.xmm.imm
.r64.xmm.imm:
.r32.xmm.imm:
.mem.xmm.imm:
    RET
  ENDP IizVEXTRACTPS::
↑ VPEXTRB
Extract Byte
Intel reference
VPEXTRB reg/m8, xmm2, imm8 VEX.128.66.0F3A 14 /r ib
VPEXTRB reg/m8, xmm2, imm8 EVEX.128.66.0F3A.WIG 14 /r ib
Category
sse41,simdint,datamov
Operands
Mb,Vdq,Ib | Rdqp,Vdq,Ib
Opcode
0x660F3A14 /r | 0x660F3A14 /r
CPU
C2++
Documented
D43
Tested by
t5294 
IizVPEXTRB:: PROC
    IiRequire SSE4.1
    IiEncoding DATA=BYTE
    IiEmitOpcode 0x14
    IiDisp8EVEX T1S8
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix VEX.128.66.0F3A, EVEX.128.66.0F3A.WIG
    IiDispatchFormat  r64.xmm.imm,r32.xmm.imm,r16.xmm.imm,r8.xmm.imm, mem.xmm.imm
.r64.xmm.imm:
.r32.xmm.imm:
.r16.xmm.imm:
.r8.xmm.imm:
.mem.xmm.imm:
    RET
  ENDP IizVPEXTRB::
↑ VPEXTRW
Extract Word
Intel reference
VPEXTRW reg, xmm1, imm8 VEX.128.66.0F C5 /r ib
VPEXTRW reg/m16, xmm2, imm8 VEX.128.66.0F3A 15 /r ib
VPEXTRW reg, xmm1, imm8 EVEX.128.66.0F.WIG C5 /r ib
VPEXTRW reg/m16, xmm2, imm8 VEX.128.66.0F3A.WIG 15 /r ib
Category
sse41,simdint,datamov
Operands
Mw,Vdq,Ib | Rdqp,Vdq,Ib | Gdqp,Nq,Ib | Gdqp,Udq,Ib
Opcode
0x660F3A15 /r | 0x660F3A15 /r | 0x0FC5 /r | 0x660FC5 /r
CPU
C2++
Documented
D43
Tested by
t5294 
IizVPEXTRW:: PROC
    IiRequire SSE4.1
    IiAllowModifier CODE
    IiDisp8EVEX T1S16
    IiEmitImm Operand3, BYTE
    IiModRM /r
    IiDispatchFormat  r64.xmm.imm,r32.xmm.imm,r16.xmm.imm,mem.xmm.imm
.mem.xmm.imm:
    IiEncoding CODE=LONG,DATA=WORD
    IiEmitOpcode 0x15
    IiEmitPrefix VEX.128.66.0F3A, EVEX.128.66.0F3A.WIG
    IiOpEn MR
    RET
.r64.xmm.imm:
.r32.xmm.imm:
.r16.xmm.imm:
    IiDispatchCode LONG=.mem.xmm.imm:
    IiEncoding CODE=SHORT,DATA=WORD
    IiEmitOpcode 0xC5
    IiEmitPrefix VEX.128.66.0F, EVEX.128.0F.WIG
    IiOpEn RM
    RET
  ENDP IizVPEXTRW::
↑ VPEXTRD
Extract Dword/Qword
Intel reference
VPEXTRD r32/m32, xmm2, imm8 VEX.128.66.0F3A.W0 16 /r ib
VPEXTRD r32/m32, xmm2, imm8 EVEX.128.66.0F3A.W0 16 /r ib
Category
sse41,simdint,datamov
Operands
Ed,Vdq,Ib
Opcode
0x660F3A16 /r
CPU
C2++
Documented
D43
Tested by
t5294 
IizVPEXTRD:: PROC
    IiRequire SSE4.1
    IiEmitOpcode 0x16
    IiEncoding DATA=DWORD
    IiDisp8EVEX T1S32
    IiOpEn MR 
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix VEX.128.66.0F3A.W0, EVEX.128.66.0F3A.W0
    IiDispatchFormat  r32.xmm.imm,r64.xmm.imm,mem.xmm.imm
.r64.xmm.imm:
.r32.xmm.imm:
.mem.xmm.imm:
    RET
  ENDP IizVPEXTRD::
↑ VPEXTRQ
Extract Dword/Qword
Intel reference
VPEXTRQ r64/m64, xmm2, imm8 VEX.128.66.0F3A.W1 16 /r ib
VPEXTRQ r64/m64, xmm2, imm8 EVEX.128.66.0F3A.W1 16 /r ib
Category
sse41,simdint,datamov
Operands
Eqp,Vdq,Ib
Opcode
0x660F3A16 /r
CPU
C2++
Documented
D43
Tested by
t5294 
IizVPEXTRQ:: PROC
    IiRequire SSE4.1
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x16
    IiDisp8EVEX T1S64
    IiOpEn MR
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix VEX.128.66.0F3A.W1, EVEX.128.66.0F3A.W1
    IiDispatchFormat  r64.xmm.imm, mem.xmm.imm
.r64.xmm.imm:
.mem.xmm.imm:
    RET
  ENDP IizVPEXTRQ::
↑ VINSERTF32X4
Insert Packed Floating-Point Values
Intel reference
VINSERTF32X4 ymm1 {k1}{z}, ymm2, xmm3/m128, imm8 EVEX.NDS.256.66.0F3A.W0 18 /r ib
VINSERTF32X4 zmm1 {k1}{z}, zmm2, xmm3/m128, imm8 EVEX.NDS.512.66.0F3A.W0 18 /r ib
Opcode
0x18
Tested by
t5296 
IizVINSERTF32X4:: PROC
    IiEmitOpcode 0x18
.op:IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiDisp8EVEX T2F64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  ymm.ymm.xmm.imm, ymm.ymm.mem.imm, zmm.zmm.xmm.imm, zmm.zmm.mem.imm
.ymm.ymm.xmm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W0
    RET
.zmm.zmm.xmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W0
    RET
  ENDP IizVINSERTF32X4::
↑ VINSERTI32X4
Insert Packed Integer Values
Intel reference
VINSERTI32X4 ymm1 {k1}{z}, ymm2, xmm3/m128, imm8 EVEX.NDS.256.66.0F3A.W0 38 /r ib
VINSERTI32X4 zmm1 {k1}{z}, zmm2, xmm3/m128, imm8 EVEX.NDS.512.66.0F3A.W0 38 /r ib
Opcode
0x38
Tested by
t5298 
IizVINSERTI32X4:: PROC
    IiEmitOpcode 0x38
    JMP IizVINSERTF32X4.op:
  ENDP IizVINSERTI32X4::
↑ VINSERTF32X8
Insert Packed Floating-Point Values
Intel reference
VINSERTF32X8 zmm1 {k1}{z}, zmm2, ymm3/m256, imm8 EVEX.NDS.512.66.0F3A.W0 1A /r ib
Opcode
0x1A
Tested by
t5296 
IizVINSERTF32X8:: PROC
    IiEmitOpcode 0x1A
.op:IiAllowModifier MASK
    IiEncoding DATA=DWORD
    IiDisp8EVEX T4F64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W0
    IiDispatchFormat  zmm.zmm.ymm.imm, zmm.zmm.mem.imm
.zmm.zmm.ymm.imm:
.zmm.zmm.mem.imm:
    RET
  ENDP IizVINSERTF32X8::
↑ VINSERTI32X8
Insert Packed Integer Values
Intel reference
VINSERTI32X8 zmm1 {k1}{z}, zmm2, ymm3/m256, imm8 EVEX.NDS.512.66.0F3A.W0 3A /r ib
Opcode
0x3A
Tested by
t5298 
IizVINSERTI32X8:: PROC
    IiEmitOpcode 0x3A
    JMP IizVINSERTF32X8.op:
  ENDP IizVINSERTI32X8::
↑ VINSERTF64X2
Insert Packed Floating-Point Values
Intel reference
VINSERTF64X2 ymm1 {k1}{z}, ymm2, xmm3/m128, imm8 EVEX.NDS.256.66.0F3A.W1 18 /r ib
VINSERTF64X2 zmm1 {k1}{z}, zmm2, xmm3/m128, imm8 EVEX.NDS.512.66.0F3A.W1 18 /r ib
Opcode
0x18
Tested by
t5296 
IizVINSERTF64X2:: PROC
    IiEmitOpcode 0x18
.op:IiAllowModifier MASK
    IiEncoding DATA=QWORD
    IiDisp8EVEX T2F64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  ymm.ymm.xmm.imm, ymm.ymm.mem.imm, zmm.zmm.xmm.imm, zmm.zmm.mem.imm
.ymm.ymm.xmm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W1
    RET
.zmm.zmm.xmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W1
    RET
  ENDP IizVINSERTF64X2::
↑ VINSERTI64X2
Insert Packed Integer Values
Intel reference
VINSERTI64X2 ymm1 {k1}{z}, ymm2, xmm3/m128, imm8 EVEX.NDS.256.66.0F3A.W1 38 /r ib
VINSERTI64X2 zmm1 {k1}{z}, zmm2, xmm3/m128, imm8 EVEX.NDS.512.66.0F3A.W1 38 /r ib
Opcode
0x38
Tested by
t5298 
IizVINSERTI64X2:: PROC
    IiEmitOpcode 0x38
    JMP IizVINSERTF64X2.op:
  ENDP IizVINSERTI64X2::
↑ VINSERTF64X4
Insert Packed Floating-Point Values
Intel reference
VINSERTF64X4 zmm1 {k1}{z}, zmm2, ymm3/m256, imm8 EVEX.NDS.512.66.0F3A.W1 1A /r ib
Opcode
0x1A
Tested by
t5296 
IizVINSERTF64X4:: PROC
    IiEmitOpcode 0x1A
.op:IiAllowModifier MASK
    IiEncoding DATA=QWORD
    IiDisp8EVEX T4F64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W1
    IiDispatchFormat  zmm.zmm.ymm.imm, zmm.zmm.mem.imm
.zmm.zmm.ymm.imm:
.zmm.zmm.mem.imm:
    RET
  ENDP IizVINSERTF64X4::
↑ VINSERTI64X4
Insert Packed Integer Values
Intel reference
VINSERTI64X4 zmm1 {k1}{z}, zmm2, ymm3/m256, imm8 EVEX.NDS.512.66.0F3A.W1 3A /r ib
Opcode
0x3A
Tested by
t5298 
IizVINSERTI64X4:: PROC
    IiEmitOpcode 0x3A
    JMP IizVINSERTF64X4.op:
  ENDP IizVINSERTI64X4::
↑ VINSERTF128
Insert Packed Floating-Point Values
Description
VINSERTF128
Intel reference
VINSERTF128 ymm1, ymm2, xmm3/m128, imm8 VEX.NDS.256.66.0F3A.W0 18 /r ib
Opcode
0x18
Tested by
t5296 
IizVINSERTF128:: PROC
    IiEmitOpcode 0x18
.op:IiEncoding DATA=OWORD
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.256.66.0F3A.W0
    IiDispatchFormat  ymm.ymm.xmm.imm, ymm.ymm.mem.imm
.ymm.ymm.xmm.imm:
.ymm.ymm.mem.imm:
    RET
  ENDP IizVINSERTF128::
↑ VINSERTI128
Insert Packed Integer Values
Description
VINSERTI128
Intel reference
VINSERTI128 ymm1, ymm2, xmm3/m128, imm8 VEX.NDS.256.66.0F3A.W0 38 /r ib
Opcode
0x38
Tested by
t5298 
IizVINSERTI128:: PROC
    IiEmitOpcode 0x38
    JMP IizVINSERTF128.op:
  ENDP IizVINSERTI128::
↑ VINSERTPS
Insert Packed Single-FP Value
Intel reference
VINSERTPS xmm1, xmm2, xmm3/m32, imm8 VEX.NDS.128.66.0F3A.WIG 21 /r ib
VINSERTPS xmm1, xmm2, xmm3/m32, imm8 EVEX.NDS.128.66.0F3A.W0 21 /r ib
Category
sse41,simdfp,datamov
Operands
Vps,Ups,Ib | Vps,Md,Ib
Opcode
0x660F3A21 /r | 0x660F3A21 /r
CPU
C2++
Documented
D43
Tested by
t5302 
IizVINSERTPS:: PROC
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x21
    IiDisp8EVEX T1S32
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.128.66.0F3A.WIG, EVEX.NDS.128.66.0F3A.W0
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVINSERTPS::
↑ VPINSRB
Insert Byte
Intel reference
VPINSRB xmm1, xmm2, r32/m8, imm8 VEX.NDS.128.66.0F3A 20 /r ib
VPINSRB xmm1, xmm2, r32/m8, imm8 EVEX.NDS.128.66.0F3A.WIG 20 /r ib
Category
sse41,simdint,datamov
Operands
Vdq,Mb,Ib | Vdq,Rdqp,Ib
Opcode
0x660F3A20 /r | 0x660F3A20 /r
CPU
C2++
Documented
D43
Tested by
t5302 
IizVPINSRB:: PROC
    IiEncoding DATA=BYTE
    IiEmitOpcode 0x20
    IiDisp8EVEX T1S8
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.128.66.0F3A, EVEX.NDS.128.66.0F3A.WIG
    IiDispatchFormat  xmm.xmm.r32.imm, xmm.xmm.mem.imm
.xmm.xmm.r32.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVPINSRB::
↑ VPINSRW
Insert Word
Intel reference
VPINSRW xmm1, xmm2, r32/m16, imm8 VEX.NDS.128.66.0F C4 /r ib
VPINSRW xmm1, xmm2, r32/m16, imm8 EVEX.NDS.128.66.0F.WIG C4 /r ib
Category
sse1,simdint
Operands
Pq,Rdqp,Ib | Pq,Mw,Ib | Vdq,Rdqp,Ib | Vdq,Mw,Ib
Opcode
0x0FC4 /r | 0x0FC4 /r | 0x660FC4 /r | 0x660FC4 /r
CPU
P3+
Tested by
t5302 
IizVPINSRW:: PROC
    IiEncoding DATA=WORD
    IiEmitOpcode 0xC4
    IiDisp8EVEX T1S16
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.128.66.0F, EVEX.NDS.128.66.0F.WIG
    IiDispatchFormat  xmm.xmm.r32.imm, xmm.xmm.mem.imm
.xmm.xmm.r32.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVPINSRW::
↑ VPINSRD
Insert Dword/Qword
Intel reference
VPINSRD xmm1, xmm2, r32/m32, imm8 VEX.NDS.128.66.0F3A.W0 22 /r ib
VPINSRD xmm1, xmm2, r32/m32, imm8 EVEX.NDS.128.66.0F3A.W0 22 /r ib
Category
sse41,simdint,datamov
Operands
Vdq,Ed,Ib
Opcode
0x660F3A22 /r
CPU
C2++
Documented
D43
Tested by
t5302 
IizVPINSRD:: PROC
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x22
    IiDisp8EVEX T1S32
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.128.66.0F3A.W0, EVEX.NDS.128.66.0F3A.W0
    IiDispatchFormat  xmm.xmm.r32.imm, xmm.xmm.mem.imm
.xmm.xmm.r32.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVPINSRD::
↑ VPINSRQ
Insert Dword/Qword
Intel reference
VPINSRQ xmm1, xmm2, r64/m64, imm8 VEX.NDS.128.66.0F3A.W1 22 /r ib
VPINSRQ xmm1, xmm2, r64/m64, imm8 EVEX.NDS.128.66.0F3A.W1 22 /r ib
Category
sse41,simdint,datamov
Operands
Vdq,Eqp,Ib
Opcode
0x660F3A22 /r
CPU
C2++
Documented
D43
Tested by
t5302 
IizVPINSRQ:: PROC
    IiEncoding DATA=QWORD
    IiAbortIfNot64
    IiEmitOpcode 0x22
    IiDisp8EVEX T1S64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.128.66.0F3A.W1, EVEX.NDS.128.66.0F3A.W1
    IiDispatchFormat  xmm.xmm.r64.imm, xmm.xmm.mem.imm
.xmm.xmm.r64.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVPINSRQ::
↑ VFIXUPIMMSS
Fix Up Special Scalar Float32 Value
Intel reference
VFIXUPIMMSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}, imm8 EVEX.NDS.LIG.66.0F3A.W0 55 /r ib
Opcode
0x55
Tested by
t5308 
IizVFIXUPIMMSS:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Operand=DH, Register=xmm
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x55
    IiDisp8EVEX T1S32
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix EVEX.NDS.LIG.66.0F3A.W0
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVFIXUPIMMSS::
↑ VFIXUPIMMSD
Fix Up Special Scalar Float64 Value
Intel reference
VFIXUPIMMSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8 EVEX.NDS.LIG.66.0F3A.W1 55 /r ib
Opcode
0x55
Tested by
t5308 
IizVFIXUPIMMSD:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Operand=DH, Register=xmm
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x55
    IiDisp8EVEX T1S64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix EVEX.NDS.LIG.66.0F3A.W1    
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVFIXUPIMMSD::
↑ VFIXUPIMMPS
Fix Up Special Packed Float32 Values
Intel reference
VFIXUPIMMPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst, imm8 EVEX.NDS.128.66.0F3A.W0 54 /r
VFIXUPIMMPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst, imm8 EVEX.NDS.256.66.0F3A.W0 54 /r
VFIXUPIMMPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{sae}, imm8 EVEX.NDS.512.66.0F3A.W0 54 /r ib
Opcode
0x54
Tested by
t5308 
IizVFIXUPIMMPS:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD, Operand=DH
    IiAllowSuppressing Operand=DH
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x54
    IiDisp8EVEX FV32
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
    IiEmitPrefix EVEX.NDS.128.66.0F3A.W0
    RET
.ymm.ymm.mem.imm:
.ymm.ymm.ymm.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W0
    RET
.zmm.zmm.mem.imm:
.zmm.zmm.zmm.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W0
    RET
  ENDP IizVFIXUPIMMPS::
↑ VFIXUPIMMPD
Fix Up Special Packed Float64 Values
Intel reference
VFIXUPIMMPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst, imm8 EVEX.NDS.128.66.0F3A.W1 54 /r ib
VFIXUPIMMPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst, imm8 EVEX.NDS.256.66.0F3A.W1 54 /r ib
VFIXUPIMMPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{sae}, imm8 EVEX.NDS.512.66.0F3A.W1 54 /r ib
Opcode
0x54
Tested by
t5308 
IizVFIXUPIMMPD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD, Operand=DH
    IiAllowSuppressing Operand=DH
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x54
    IiDisp8EVEX FV64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
    IiEmitPrefix EVEX.NDS.128.66.0F3A.W1
    RET
.ymm.ymm.mem.imm:
.ymm.ymm.ymm.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W1
    RET
.zmm.zmm.mem.imm:
.zmm.zmm.zmm.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W1
    RET
  ENDP IizVFIXUPIMMPD::
↑ VFPCLASSSS
Tests Types Of a Scalar Float32 Values
Intel reference
VFPCLASSSS k2 {k1}, xmm2/m32, imm8 EVEX.LIG.66.0F3A.W0 67 /r ib
Opcode
0x67
Tested by
t5430 
IizVFPCLASSSS:: PROC
    IiAllowMaskMerging
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x67
    IiDisp8EVEX T1S32
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix EVEX.LIG.66.0F3A.W0
    IiDispatchFormat  krg.xmm.imm, krg.mem.imm
.krg.xmm.imm:
.krg.mem.imm:
    RET
  ENDP IizVFPCLASSSS::
↑ VFPCLASSSD
Tests Types Of a Scalar Float64 Values
Intel reference
VFPCLASSSD k2 {k1}, xmm2/m64, imm8 EVEX.LIG.66.0F3A.W1 67 /r ib
Opcode
0x67
Tested by
t5430 
IizVFPCLASSSD:: PROC
    IiAllowMaskMerging
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x67
    IiDisp8EVEX T1S64
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiEmitPrefix EVEX.LIG.66.0F3A.W1
    IiDispatchFormat  krg.xmm.imm, krg.mem.imm
.krg.xmm.imm:
.krg.mem.imm:
    RET
  ENDP IizVFPCLASSSD::
↑ VFPCLASSPS
Tests Types Of a Packed Float32 Values
Intel reference
VFPCLASSPS k2 {k1}, xmm2/m128/m32bcst, imm8 EVEX.128.66.0F3A.W0 66 /r ib
VFPCLASSPS k2 {k1}, ymm2/m256/m32bcst, imm8 EVEX.256.66.0F3A.W0 66 /r ib
VFPCLASSPS k2 {k1}, zmm2/m512/m32bcst, imm8 EVEX.512.66.0F3A.W0 66 /r ib
Opcode
0x66
Tested by
t5430 
IizVFPCLASSPS:: PROC
    IiAllowMaskMerging
    IiAllowBroadcasting DWORD, Operand=DH
    IiEmitOpcode 0x66
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDataSize Operand2, StreamingSIMD=ON
    IiDispatchFormat  krg.xmm.imm, krg.ymm.imm, krg.zmm.imm, \
    krg.m128.imm, krg.m256.imm, krg.m512.imm, krg.mem.imm
.krg.m128.imm:
.krg.xmm.imm:
    IiEmitPrefix EVEX.128.66.0F3A.W0
    RET
.krg.m256.imm:
.krg.ymm.imm:
    IiEmitPrefix EVEX.256.66.0F3A.W0
    RET
.krg.mem.imm:    
.krg.m512.imm:
.krg.zmm.imm:
    IiEmitPrefix EVEX.512.66.0F3A.W0
    RET
  ENDP IizVFPCLASSPS::
↑ VFPCLASSPD
Tests Types Of a Packed Float64 Values
Intel reference
VFPCLASSPD k2 {k1}, xmm2/m128/m64bcst, imm8 EVEX.128.66.0F3A.W1 66 /r ib
VFPCLASSPD k2 {k1}, ymm2/m256/m64bcst, imm8 EVEX.256.66.0F3A.W1 66 /r ib
VFPCLASSPD k2 {k1}, zmm2/m512/m64bcst, imm8 EVEX.512.66.0F3A.W1 66 /r ib
Opcode
0x66
IizVFPCLASSPD:: PROC
    IiAllowMaskMerging
    IiAllowBroadcasting QWORD, Operand=DH
    IiEmitOpcode 0x66
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDisp8EVEX FV64
    IiDataSize Operand2, StreamingSIMD=ON
    IiDispatchFormat  krg.xmm.imm, krg.ymm.imm, krg.zmm.imm, \
    krg.m128.imm, krg.m256.imm, krg.m512.imm, krg.mem.imm
.krg.m128.imm:
.krg.xmm.imm:
    IiEmitPrefix EVEX.128.66.0F3A.W1
    RET
.krg.m256.imm:
.krg.ymm.imm:
    IiEmitPrefix EVEX.256.66.0F3A.W1
    RET
.krg.mem.imm:    
.krg.m512.imm:
.krg.zmm.imm:
    IiEmitPrefix EVEX.512.66.0F3A.W1
    RET
  ENDP IizVFPCLASSPD::
↑ VPGATHERDD
Gather Packed Dword with Signed Dword Indices
Description
VPGATHERDD
Intel reference
VPGATHERDD xmm1, vm32x, xmm2 VEX.DDS.128.66.0F38.W0 90 /r /vsib
VPGATHERDD ymm1, vm32y, ymm2 VEX.DDS.256.66.0F38.W0 90 /r /vsib
VPGATHERDD xmm1 {k1}, vm32x EVEX.128.66.0F38.W0 90 /r /vsib
VPGATHERDD ymm1 {k1}, vm32y EVEX.256.66.0F38.W0 90 /r /vsib
VPGATHERDD zmm1 {k1}, vm32z EVEX.512.66.0F38.W0 90 /r /vsib
VPGATHERDD zmm1 {k1}, vm32z MVEX.512.66.0F38.W0 90 /r /vsib
Opcode
0x90
Tested by
t5440 
IizVPGATHERDD:: PROC          
    IiAllowMaskMerging
    IiEmitOpcode 0x90
    IiDisp8EVEX T1S32
    IiDispatchFormat  xmm.mem.xmm, ymm.mem.ymm, xmm.mem, ymm.mem, zmm.mem
.xmm.mem.xmm:
    IiEmitPrefix VEX.DDS.128.66.0F38.W0
    IiVSIB vm32x
    IiOpEn RMV
    IiModRM /r
    RET
.ymm.mem.ymm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W0
    IiVSIB vm32y
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm32x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm32y
    IiOpEn RM
    IiModRM /r
    RET
.zmm.mem:
    IiDisp8MVEX Di32
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    IiVSIB vm32z
    IiOpEn RM
    IiModRM /r
    RET
  ENDP IizVPGATHERDD::
↑ VPGATHERQD
Gather Packed Dword with Signed Qword Indices
Description
VPGATHERQD
Intel reference
VPGATHERQD xmm1, vm64x, xmm2 VEX.DDS.128.66.0F38.W0 91 /r /vsib
VPGATHERQD xmm1, vm64y, xmm2 VEX.DDS.256.66.0F38.W0 91 /r /vsib
VPGATHERQD xmm1 {k1}, vm64x EVEX.128.66.0F38.W0 91 /r /vsib
VPGATHERQD xmm1 {k1}, vm64y EVEX.256.66.0F38.W0 91 /r /vsib
VPGATHERQD ymm1 {k1}, vm64z EVEX.512.66.0F38.W0 91 /r /vsib
Opcode
0x91
Tested by
t5440 
IizVPGATHERQD:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0x91
    IiDisp8EVEX T1S32
    IiDispatchFormat  xmm.mem.xmm, xmm.mem, ymm.mem
.xmm.m256.xmm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W0
    IiVSIB vm64y
    IiOpEn RMV
    IiModRM /r
    RET    
.xmm.mem.xmm:
    JSt [EDI+II.Ppx],iiPpxVSIB2, .xmm.m256.xmm: 
    IiEmitPrefix VEX.DDS.128.66.0F38.W0
    IiVSIB vm64x
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.m256:    
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm64y
    IiOpEn RM
    IiModRM /r
    RET
.xmm.mem:
    JSt [EDI+II.Ppx],iiPpxVSIB2, .xmm.m256:
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm64x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0
    IiVSIB vm64z
    IiOpEn RM
    IiModRM /r
    RET
  ENDP IizVPGATHERQD::
↑ VPGATHERDQ
Gather Packed Qword with Signed Dword Indices
Description
VPGATHERDQ
Intel reference
VPGATHERDQ xmm1, vm32x, xmm2 VEX.DDS.128.66.0F38.W1 90 /r /vsib
VPGATHERDQ ymm1, vm32x, ymm2 VEX.DDS.256.66.0F38.W1 90 /r /vsib
VPGATHERDQ xmm1 {k1}, vm32x EVEX.128.66.0F38.W1 90 /r /vsib
VPGATHERDQ ymm1 {k1}, vm32x EVEX.256.66.0F38.W1 90 /r /vsib
VPGATHERDQ zmm1 {k1}, vm32y EVEX.512.66.0F38.W1 90 /r /vsib
VPGATHERDQ zmm1 {k1}, vm32z MVEX.512.66.0F38.W1 90 /r /vsib
Opcode
0x90
Tested by
t5440 
IizVPGATHERDQ:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0x90
    IiDisp8EVEX T1S64
    IiDispatchFormat  xmm.mem.xmm, ymm.mem.ymm, xmm.mem, ymm.mem, zmm.mem
.xmm.mem.xmm:
    IiEmitPrefix VEX.DDS.128.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RMV
    IiModRM /r
    RET
.ymm.mem.ymm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RM
    IiModRM /r
    RET
.zmm.m512:
    IiDisp8MVEX Sn64
    IiEmitPrefix MVEX.512.66.0F38.W1
    IiVSIB vm32z
    IiOpEn RM
    IiModRM /r
    RET
.zmm.mem:
    JSt [EDI+II.Ppx],iiPpxVSIB1, .zmm.m512:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiVSIB vm32y
    IiOpEn RM
    IiModRM /r
    RET    
  ENDP IizVPGATHERDQ::
↑ VPGATHERQQ
Gather Packed Qword with Signed Qword Indices
Description
VPGATHERQQ
Intel reference
VPGATHERQQ xmm1, vm64x, xmm2 VEX.DDS.128.66.0F38.W1 91 /r /vsib
VPGATHERQQ ymm1, vm64y, ymm2 VEX.DDS.256.66.0F38.W1 91 /r /vsib
VPGATHERQQ xmm1 {k1}, vm64x EVEX.128.66.0F38.W1 91 /r /vsib
VPGATHERQQ ymm1 {k1}, vm64y EVEX.256.66.0F38.W1 91 /r /vsib
VPGATHERQQ zmm1 {k1}, vm64z EVEX.512.66.0F38.W1 91 /r /vsib
Opcode
0x91
Tested by
t5440 
IizVPGATHERQQ:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0x91
    IiDisp8EVEX T1S64
    IiDispatchFormat  xmm.mem.xmm, ymm.mem.ymm, xmm.mem, ymm.mem, zmm.mem
.xmm.mem.xmm:
    IiEmitPrefix VEX.DDS.128.66.0F38.W1
    IiVSIB vm64x
    IiOpEn RMV
    IiModRM /r
    RET
.ymm.mem.ymm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W1
    IiVSIB vm64y
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm64x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm64y
    IiOpEn RM
    IiModRM /r
    RET
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiVSIB vm64z
    IiOpEn RM
    IiModRM /r
    RET
  ENDP IizVPGATHERQQ::
↑ VGATHERDPS
Gather Packed Single with Signed Dword Indices
Description
VGATHERDPS
Intel reference
VGATHERDPS xmm1, vm32x, xmm2 VEX.DDS.128.66.0F38.W0 92 /r /vsib
VGATHERDPS ymm1, vm32y, ymm2 VEX.DDS.256.66.0F38.W0 92 /r /vsib
VGATHERDPS xmm1 {k1}, vm32x EVEX.128.66.0F38.W0 92 /r /vsib
VGATHERDPS ymm1 {k1}, vm32y EVEX.256.66.0F38.W0 92 /r /vsib
VGATHERDPS zmm1 {k1}, vm32z EVEX.512.66.0F38.W0 92 /r /vsib
VGATHERDPS zmm1 {k1}, vm32z MVEX.512.66.0F38.W0 92 /r /vsib
Opcode
0x92
Tested by
t5442 
IizVGATHERDPS:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0x92
    IiDisp8EVEX T1S32
    IiDispatchFormat  xmm.mem.xmm, ymm.mem.ymm, xmm.mem, ymm.mem, zmm.mem
.xmm.mem.xmm:
    IiEmitPrefix VEX.DDS.128.66.0F38.W0
    IiVSIB vm32x
    IiOpEn RMV
    IiModRM /r
    RET
.ymm.mem.ymm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W0
    IiVSIB vm32y
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm32x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm32y
    IiOpEn RM
    IiModRM /r
    RET
.zmm.mem:
    IiDisp8MVEX Df32
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    IiVSIB vm32z
    IiOpEn RM
    IiModRM /r
    RET
  ENDP IizVGATHERDPS::
↑ VGATHERDPD
Gather Packed Double with Signed Dword Indices
Description
VGATHERDPD
Intel reference
VGATHERDPD xmm1, vm32x, xmm2 VEX.DDS.128.66.0F38.W1 92 /r /vsib
VGATHERDPD ymm1, vm32x, ymm2 VEX.DDS.256.66.0F38.W1 92 /r /vsib
VGATHERDPD xmm1 {k1}, vm32x EVEX.128.66.0F38.W1 92 /r /vsib
VGATHERDPD ymm1 {k1}, vm32x EVEX.256.66.0F38.W1 92 /r /vsib
VGATHERDPD zmm1 {k1}, vm32y EVEX.512.66.0F38.W1 92 /r /vsib
VGATHERDPD zmm1 {k1}, vm32z MVEX.512.66.0F38.W1 92 /r /vsib
Opcode
0c92
Tested by
t5442 
IizVGATHERDPD:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0x92
    IiDisp8EVEX T1S64
    IiDispatchFormat  xmm.mem.xmm, ymm.mem.ymm, xmm.mem, ymm.mem, zmm.mem
.xmm.mem.xmm:
    IiEmitPrefix VEX.DDS.128.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RMV
    IiModRM /r
    RET
.ymm.mem.ymm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm32x
    IiOpEn RM
    IiModRM /r
    RET
.zmm.m512:
    IiDisp8MVEX Sn64
    IiEmitPrefix MVEX.512.66.0F38.W1
    IiVSIB vm32z
    IiOpEn RM
    IiModRM /r
    RET
.zmm.mem:
    JSt [EDI+II.Ppx],iiPpxVSIB1, .zmm.m512:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiOpEn RM
    IiVSIB vm32y
    IiModRM /r
    RET
  ENDP IizVGATHERDPD::
↑ VGATHERQPS
Gather Packed Single with Signed Qword Indices
Description
VGATHERQPS
Intel reference
VGATHERQPS xmm1, vm64x, xmm2 VEX.DDS.128.66.0F38.W0 93 /r /vsib
VGATHERQPS xmm1, vm64y, xmm2 VEX.DDS.256.66.0F38.W0 93 /r /vsib
VGATHERQPS xmm1 {k1}, vm64x EVEX.128.66.0F38.W0 93 /r /vsib
VGATHERQPS xmm1 {k1}, vm64y EVEX.256.66.0F38.W0 93 /r /vsib
VGATHERQPS ymm1 {k1}, vm64z EVEX.512.66.0F38.W0 93 /r /vsib
Opcode
0x93
Tested by
t5442 
IizVGATHERQPS:: PROC
    IiAllowMaskMerging 
    IiEmitOpcode 0x93
    IiDisp8EVEX T1S32
    IiDispatchFormat  xmm.mem.xmm, xmm.mem, ymm.mem
.xmm.m256.xmm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W0
    IiVSIB vm64y
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.mem.xmm:
    JSt [EDI+II.Ppx],iiPpxVSIB2, .xmm.m256.xmm:
    IiEmitPrefix VEX.DDS.128.66.0F38.W0
    IiVSIB vm64x
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.m256:
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm64y
    IiOpEn RM
    IiModRM /r
    RET
.xmm.mem:
    JSt [EDI+II.Ppx],iiPpxVSIB2, .xmm.m256:
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm64x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0
    IiVSIB vm64z
    IiOpEn RM
    IiModRM /r
    RET
  ENDP IizVGATHERQPS::
↑ VGATHERQPD
Gather Packed Double with Signed Qword Indices
Description
VGATHERQPD
Intel reference
VGATHERQPD xmm1, vm64x, xmm2 VEX.DDS.128.66.0F38.W1 93 /r /vsib
VGATHERQPD ymm1, vm64y, ymm2 VEX.DDS.256.66.0F38.W1 93 /r /vsib
VGATHERQPD xmm1 {k1}, vm64x EVEX.128.66.0F38.W1 93 /r /vsib
VGATHERQPD ymm1 {k1}, vm64y EVEX.256.66.0F38.W1 93 /r /vsib
VGATHERQPD zmm1 {k1}, vm64z EVEX.512.66.0F38.W1 93 /r /vsib
Opcode
0x93
Tested by
t5442 
IizVGATHERQPD:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0x93
    IiDisp8EVEX T1S64
    IiDispatchFormat  xmm.mem.xmm, ymm.mem.ymm, xmm.mem, ymm.mem, zmm.mem
.xmm.mem.xmm:
    IiEmitPrefix VEX.DDS.128.66.0F38.W1
    IiVSIB vm64x
    IiOpEn RMV
    IiModRM /r
    RET
.ymm.mem.ymm:
    IiEmitPrefix VEX.DDS.256.66.0F38.W1
    IiVSIB vm64y
    IiOpEn RMV
    IiModRM /r
    RET
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm64x
    IiOpEn RM
    IiModRM /r
    RET
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm64y
    IiOpEn RM
    IiModRM /r
    RET
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiVSIB vm64z
    IiOpEn RM
    IiModRM /r
    RET
  ENDP IizVGATHERQPD::
↑ VGATHERPF0DPS
Sparse Prefetch Packed SP Data Values with Signed Dword Indices Using T0 Hint
Intel reference
VGATHERPF0DPS vm32z {k1} EVEX.512.66.0F38.W0 C6 /1 /vsib
VGATHERPF0DPS vm32z {k1} MVEX.512.66.0F38.W0 C6 /1 /vsib
Opcode
0xC6
Tested by
t5444 
IizVGATHERPF0DPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S32
     IiDisp8MVEX Df32
     IiOpEn M
     IiVSIB vm32z
     IiModRM /1
     IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF0DPS::
↑ VGATHERPF0HINTDPS
Sparse Prefetch Packed SP Data Values with Signed Dword Indices Using T0 Hint
Intel reference
VGATHERPF0HINTDPS vm32z {k1} MVEX.512.66.0F38.W0 C6 /0 /vsib
Opcode
0xC6
Tested by
t5444 
IizVGATHERPF0HINTDPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8MVEX Df32
     IiOpEn M
     IiVSIB vm32z
     IiModRM /0
     IiEmitPrefix MVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF0HINTDPS::
↑ VGATHERPF0QPS
Sparse Prefetch Packed SP Data Values with Signed Qword Indices Using T0 Hint
Intel reference
VGATHERPF0QPS vm64z {k1} EVEX.512.66.0F38.W0 C7 /1 /vsib
Opcode
0xC7
Tested by
t5444 
IizVGATHERPF0QPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S32
     IiOpEn M
     IiVSIB vm64z
     IiModRM /1
     IiEmitPrefix EVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF0QPS::
↑ VGATHERPF0DPD
Sparse Prefetch Packed DP Data Values with Signed Dword Indices Using T0 Hint
Intel reference
VGATHERPF0DPD vm32y {k1} EVEX.512.66.0F38.W1 C6 /1 /vsib
Opcode
0xC6
Tested by
t5444 
IizVGATHERPF0DPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm32y
     IiModRM /1
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF0DPD::
↑ VGATHERPF0HINTDPD
Sparse Prefetch Packed DP Data Values with Signed Dword Indices Using T0 Hint
Intel reference
VGATHERPF0HINTDPD vm32z {k1} MVEX.512.66.0F38.W1 C6 /0 /vsib
Opcode
0xC6
Tested by
t5444 
IizVGATHERPF0HINTDPD:: PROC
     IiAllowMaskMerging
     IiDisp8MVEX Sn64
     IiEmitOpcode 0xC6
     IiOpEn M
     IiVSIB vm32z
     IiModRM /0
     IiEmitPrefix MVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF0HINTDPD::
↑ VGATHERPF0QPD
Sparse Prefetch Packed DP Data Values with Signed Qword Indices Using T0 Hint
Intel reference
VGATHERPF0QPD vm64z {k1} EVEX.512.66.0F38.W1 C7 /1 /vsib
Opcode
0xC7
Tested by
t5444 
IizVGATHERPF0QPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm64z
     IiModRM /1
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF0QPD::
↑ VGATHERPF1DPS
Sparse Prefetch Packed SP Data Values with Signed Dword Indices Using T1 Hint
Intel reference
VGATHERPF1DPS vm32z {k1} EVEX.512.66.0F38.W0 C6 /2 /vsib
VGATHERPF1DPS vm32z {k1} MVEX.512.66.0F38.W0 C6 /2 /vsib
Opcode
0xC6
Tested by
t5446 
IizVGATHERPF1DPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S32
     IiDisp8MVEX Df32
     IiOpEn M
     IiVSIB vm32z
     IiModRM /2
     IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF1DPS::
↑ VGATHERPF1QPS
Sparse Prefetch Packed SP Data Values with Signed Qword Indices Using T1 Hint
Intel reference
VGATHERPF1QPS vm64z {k1} EVEX.512.66.0F38.W0 C7 /2 /vsib
Opcode
0xC7
Tested by
t5446 
IizVGATHERPF1QPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S32
     IiOpEn M
     IiVSIB vm64z
     IiModRM /2
     IiEmitPrefix EVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF1QPS::
↑ VGATHERPF1DPD
Sparse Prefetch Packed DP Data Values with Signed Dword Indices Using T1 Hint
Intel reference
VGATHERPF1DPD vm32y {k1} EVEX.512.66.0F38.W1 C6 /2 /vsib
Opcode
0xC6
Tested by
t5446 
IizVGATHERPF1DPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm32y
     IiModRM /2
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF1DPD::
↑ VGATHERPF1QPD
Sparse Prefetch Packed DP Data Values with Signed Qword Indices Using T1 Hint
Intel reference
VGATHERPF1QPD vm64z {k1} EVEX.512.66.0F38.W1 C7 /2 /vsib
Opcode
0xC7
Tested by
t5446 
IizVGATHERPF1QPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm64z
     IiModRM /2
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVGATHERPF1QPD::
↑ VPSCATTERDD
Scatter Packed Dword with Signed Dword Indices
Intel reference
VPSCATTERDD vm32x {k1}, xmm1 EVEX.128.66.0F38.W0 A0 /r /vsib
VPSCATTERDD vm32y {k1}, ymm1 EVEX.256.66.0F38.W0 A0 /r /vsib
VPSCATTERDD vm32z {k1}, zmm1 EVEX.512.66.0F38.W0 A0 /r /vsib
VPSCATTERDD vm32z {k1}, zmm1 MVEX.512.66.0F38.W0 A0 /r /vsib
Opcode
0xA0
Tested by
t5450 
IizVPSCATTERDD:: PROC
    IiAllowMaskMerging
    IiDisp8EVEX T1S32
    IiEmitOpcode 0xA0
    IiOpEn MR
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm32x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm32y
    IiModRM /r
    RET
.mem.zmm:
    IiDisp8MVEX Di32
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    IiVSIB vm32z
    IiModRM /r
    RET
  ENDP IizVPSCATTERDD::
↑ VPSCATTERDQ
Scatter Packed Qword with Signed Dword Indices
Intel reference
VPSCATTERDQ vm32x {k1}, xmm1 EVEX.128.66.0F38.W1 A0 /r /vsib
VPSCATTERDQ vm32x {k1}, ymm1 EVEX.256.66.0F38.W1 A0 /r /vsib
VPSCATTERDQ vm32y {k1}, zmm1 EVEX.512.66.0F38.W1 A0 /r /vsib
VPSCATTERDQ vm32z {k1}, zmm1 MVEX.512.66.0F38.W1 A0 /r /vsib
Opcode
0xA0
Tested by
t5450 
IizVPSCATTERDQ:: PROC
    IiAllowModifier MASK
    IiDisp8EVEX T1S64
    IiOpEn MR
    IiEmitOpcode 0xA0
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm32x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm32x
    IiModRM /r
    RET
.mem.zmm:
    JSt [EDI+II.Ppx],iiPpxVSIB1, .m512.zmm:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiVSIB vm32y
    IiModRM /r
    RET
.m512.zmm:
    IiDisp8MVEX Sn64
    IiEmitPrefix MVEX.512.66.0F38.W1
    IiVSIB vm32z
    IiModRM /r
    RET
  ENDP IizVPSCATTERDQ::
↑ VPSCATTERQD
Scatter Packed Dword with Signed Qword Indices
Intel reference
VPSCATTERQD vm64x {k1}, xmm1 EVEX.128.66.0F38.W0 A1 /r /vsib
VPSCATTERQD vm64y {k1}, xmm1 EVEX.256.66.0F38.W0 A1 /r /vsib
VPSCATTERQD vm64z {k1}, ymm1 EVEX.512.66.0F38.W0 A1 /r /vsib
Opcode
0xA1
Tested by
t5450 
IizVPSCATTERQD:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0xA1
    IiDisp8EVEX T1S32
    IiOpEn MR
    IiDispatchFormat  mem.xmm, mem.ymm
.m256.xmm:
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm64y
    IiModRM /r
    RET
.mem.xmm:
    JSt [EDI+II.Ppx],iiPpxVSIB2, .m256.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm64x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.512.66.0F38.W0
    IiVSIB vm64z
    IiModRM /r
    RET
  ENDP IizVPSCATTERQD::
↑ VPSCATTERQQ
Scatter Packed Qword with Signed Qword Indices
Intel reference
VPSCATTERQQ vm64x {k1}, xmm1 EVEX.128.66.0F38.W1 A1 /r /vsib
VPSCATTERQQ vm64y {k1}, ymm1 EVEX.256.66.0F38.W1 A1 /r /vsib
VPSCATTERQQ vm64z {k1}, zmm1 EVEX.512.66.0F38.W1 A1 /r /vsib
Opcode
0xA1
Tested by
t5450 
IizVPSCATTERQQ:: PROC
    IiAllowModifier MASK
    IiEmitOpcode 0xA1
    IiDisp8EVEX T1S64
    IiOpEn MR
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm64x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm64y
    IiModRM /r
    RET
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiVSIB vm64z
    IiModRM /r
    RET
  ENDP IizVPSCATTERQQ::
↑ VSCATTERDPS
Scatter Packed Single with Signed Dword Indices
Intel reference
VSCATTERDPS vm32x {k1}, xmm1 EVEX.128.66.0F38.W0 A2 /r /vsib
VSCATTERDPS vm32y {k1}, ymm1 EVEX.256.66.0F38.W0 A2 /r /vsib
VSCATTERDPS vm32z {k1}, zmm1 EVEX.512.66.0F38.W0 A2 /r /vsib
VSCATTERDPS vm32z {k1}, zmm1 MVEX.512.66.0F38.W0 A2 /r /vsib
Opcode
0xA2
Tested by
t5452 
IizVSCATTERDPS:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0xA2
    IiDisp8EVEX T1S32
    IiOpEn MR
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm32x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm32y
    IiModRM /r
    RET
.mem.zmm:
    IiDisp8MVEX Df32
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    IiVSIB vm32z
    IiModRM /r
    RET
  ENDP IizVSCATTERDPS::
↑ VSCATTERDPD
Scatter Packed Double with Signed Dword Indices
Intel reference
VSCATTERDPD vm32x {k1}, xmm1 EVEX.128.66.0F38.W1 A2 /r /vsib
VSCATTERDPD vm32x {k1}, ymm1 EVEX.256.66.0F38.W1 A2 /r /vsib
VSCATTERDPD vm32y {k1}, zmm1 EVEX.512.66.0F38.W1 A2 /r /vsib
VSCATTERDPD vm32z {k1}, zmm1 MVEX.512.66.0F38.W1 A2 /r /vsib
Opcode
0xA2
Tested by
t5452 
IizVSCATTERDPD:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0xA2
    IiDisp8EVEX T1S64
    IiDisp8MVEX Sn64
    IiOpEn MR
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm32x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm32x
    IiModRM /r
    RET
.m512.zmm:
    IiEmitPrefix  MVEX.512.66.0F38.W1
    IiVSIB vm32z
    IiModRM /r
    RET
.mem.zmm:
    JSt [EDI+II.Ppx],iiPpxVSIB1, .m512.zmm:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiVSIB vm32y
    IiModRM /r
    RET
  ENDP IizVSCATTERDPD::
↑ VSCATTERQPS
Scatter Packed Single with Signed Qword Indices
Intel reference
VSCATTERQPS vm64x {k1}, xmm1 EVEX.128.66.0F38.W0 A3 /r /vsib
VSCATTERQPS vm64y {k1}, xmm1 EVEX.256.66.0F38.W0 A3 /r /vsib
VSCATTERQPS vm64z {k1}, ymm1 EVEX.512.66.0F38.W0 A3 /r /vsib
Opcode
0xA3
Tested by
t5452 
IizVSCATTERQPS:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0xA3
    IiDisp8EVEX T1S32
    IiOpEn MR
    IiDispatchFormat  mem.xmm, mem.ymm
.m256.xmm:    
    IiEmitPrefix EVEX.256.66.0F38.W0
    IiVSIB vm64y
    IiModRM /r
    RET
.mem.xmm:
    JSt [EDI+II.Ppx],iiPpxVSIB2, .m256.xmm: 
    IiEmitPrefix EVEX.128.66.0F38.W0
    IiVSIB vm64x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.512.66.0F38.W0
    IiVSIB vm64z
    IiModRM /r
    RET
  ENDP IizVSCATTERQPS::
↑ VSCATTERQPD
Scatter Packed Double with Signed Qword Indices
Intel reference
VSCATTERQPD vm64x {k1}, xmm1 EVEX.128.66.0F38.W1 A3 /r /vsib
VSCATTERQPD vm64y {k1}, ymm1 EVEX.256.66.0F38.W1 A3 /r /vsib
VSCATTERQPD vm64z {k1}, zmm1 EVEX.512.66.0F38.W1 A3 /r /vsib
Opcode
0xA3
Tested by
t5452 
IizVSCATTERQPD:: PROC
    IiAllowMaskMerging
    IiEmitOpcode 0xA3
    IiDisp8EVEX T1S64
    IiOpEn MR
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F38.W1
    IiVSIB vm64x
    IiModRM /r
    RET
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F38.W1
    IiVSIB vm64y
    IiModRM /r
    RET
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F38.W1
    IiVSIB vm64z
    IiModRM /r
    RET
  ENDP IizVSCATTERQPD::
↑ VSCATTERPF0DPS
Sparse Prefetch Packed SP Data Values with Signed Dword Indices Using T0 Hint with Intent to Write
Intel reference
VSCATTERPF0DPS vm32z {k1} EVEX.512.66.0F38.W0 C6 /5 /vsib
VSCATTERPF0DPS vm32z {k1} MVEX.512.66.0F38.W0 C6 /5 /vsib
Opcode
0xC6
Tested by
t5454 
IizVSCATTERPF0DPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S32
     IiDisp8MVEX Df32
     IiOpEn M
     IiVSIB vm32z
     IiModRM /5
     IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF0DPS::
↑ VSCATTERPF0HINTDPS
Sparse Prefetch Packed SP Data Values with Signed Dword Indices Using T0 Hint with Intent to Write
Intel reference
VSCATTERPF0HINTDPS vm32z {k1} MVEX.512.66.0F38.W0 C6 /4 /vsib
Opcode
0xC6
Tested by
t5454 
IizVSCATTERPF0HINTDPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8MVEX Df32
     IiOpEn M
     IiVSIB vm32z
     IiModRM /4
     IiEmitPrefix MVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF0HINTDPS::
↑ VSCATTERPF0QPS
Sparse Prefetch Packed SP Data Values with Signed Qword Indices Using T0 Hint with Intent to Write
Intel reference
VSCATTERPF0QPS vm64z {k1} EVEX.512.66.0F38.W0 C7 /5 /vsib
Operands
0xC7
Tested by
t5454 
IizVSCATTERPF0QPS:: PROC
     IiAllowModifier MASK
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S32
     IiOpEn M
     IiVSIB vm64z
     IiModRM /5
     IiEmitPrefix EVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF0QPS::
↑ VSCATTERPF0DPD
Sparse Prefetch Packed DP Data Values with Signed Dword Indices Using T0 Hint with Intent to Write
Intel reference
VSCATTERPF0DPD vm32y {k1} EVEX.512.66.0F38.W1 C6 /5 /vsib
Opcode
0xC6
Tested by
t5454 
IizVSCATTERPF0DPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm64y
     IiModRM /5
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF0DPD::
↑ VSCATTERPF0HINTDPD
Sparse Prefetch Packed DP Data Values with Signed Dword Indices Using T0 Hint with Intent to Write
Intel reference
VSCATTERPF0HINTDPD vm32z {k1} MVEX.512.66.0F38.W1 C6 /4 /vsib
Opcode
0xC6
Tested by
t5454 
IizVSCATTERPF0HINTDPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8MVEX Sn64
     IiOpEn M
     IiVSIB vm32z
     IiModRM /4
     IiEmitPrefix MVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF0HINTDPD::
↑ VSCATTERPF0QPD
Sparse Prefetch Packed DP Data Values with Signed Qword Indices Using T0 Hint with Intent to Write
Intel reference
VSCATTERPF0QPD vm64z {k1} EVEX.512.66.0F38.W1 C7 /5 /vsib
Opcode
0xC7
Tested by
t5454 
IizVSCATTERPF0QPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm64z
     IiModRM /5
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF0QPD::
↑ VSCATTERPF1DPS
Sparse Prefetch Packed SP Data Values with Signed Dword Indices Using T1 Hint with Intent to Write
Intel reference
VSCATTERPF1DPS vm32z {k1} EVEX.512.66.0F38.W0 C6 /6 /vsib
VSCATTERPF1DPS vm32z {k1} MVEX.512.66.0F38.W0 C6 /6 /vsib
Opcode
0xC6
Tested by
t5456 
IizVSCATTERPF1DPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S32
     IiDisp8MVEX Df32
     IiOpEn M
     IiVSIB vm32z
     IiModRM /6
     IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF1DPS::
↑ VSCATTERPF1QPS
Sparse Prefetch Packed SP Data Values with Signed Qword Indices Using T1 Hint with Intent to Write
Intel reference
VSCATTERPF1QPS vm64z {k1} EVEX.512.66.0F38.W0 C7 /6 /vsib
Opcode
0xC7
Tested by
t5456 
IizVSCATTERPF1QPS:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S32
     IiOpEn M
     IiVSIB vm64z
     IiModRM /6
     IiEmitPrefix EVEX.512.66.0F38.W0
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF1QPS::
↑ VSCATTERPF1DPD
Sparse Prefetch Packed DP Data Values with Signed Dword Indices Using T1 Hint with Intent to Write
Intel reference
VSCATTERPF1DPD vm32y {k1} EVEX.512.66.0F38.W1 C6 /6 /vsib
Opcode
0xC6
Tested by
t5456 
IizVSCATTERPF1DPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC6
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm32y
     IiModRM /6
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF1DPD::
↑ VSCATTERPF1QPD
Sparse Prefetch Packed DP Data Values with Signed Qword Indices Using T1 Hint with Intent to Write
Intel reference
VSCATTERPF1QPD vm64z {k1} EVEX.512.66.0F38.W1 C7 /6 /vsib
Opcode
0xC7
Tested by
t5456 
IizVSCATTERPF1QPD:: PROC
     IiAllowMaskMerging
     IiEmitOpcode 0xC7
     IiDisp8EVEX T1S64
     IiOpEn M
     IiVSIB vm64z
     IiModRM /6
     IiEmitPrefix EVEX.512.66.0F38.W1
     IiDispatchFormat  mem
.mem:RET
  ENDP IizVSCATTERPF1QPD::
↑ VGETEXPSS
Convert Exponents of Scalar SP FP Values to SP FP Value
Intel reference
VGETEXPSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae} EVEX.NDS.LIG.66.0F38.W0 43 /r
Opcode
0x43
Tested by
t5460 
IizVGETEXPSS:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Register=xmm
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x43
    IiDisp8EVEX T1S32
    IiOpEn RVM
    IiModRM /r
    IiEmitPrefix EVEX.NDS.LIG.66.0F38.W0
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
  ENDP IizVGETEXPSS::
↑ VGETEXPSD
Convert Exponents of Scalar DP FP Values to DP FP Value
Intel reference
VGETEXPSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae} EVEX.NDS.LIG.66.0F38.W1 43 /r
Opcode
0x43
Tested by
t5460 
IizVGETEXPSD:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Register=xmm
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x43
    IiDisp8EVEX T1S64
    IiOpEn RVM
    IiModRM /r
    IiEmitPrefix EVEX.NDS.LIG.66.0F38.W1
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    RET
  ENDP IizVGETEXPSD::
↑ VGETEXPPS
Convert Exponents of Packed SP FP Values to SP FP Values
Intel reference
VGETEXPPS xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.66.0F38.W0 42 /r
VGETEXPPS ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.66.0F38.W0 42 /r
VGETEXPPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae} EVEX.512.66.0F38.W0 42 /r
VGETEXPPS zmm1 {k1}, zmm2/m512/m32bcst{sae} MVEX.512.66.0F38.W0 42 /r
Opcode
0x42
Tested by
t5460 
IizVGETEXPPS:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiAllowSuppressing 
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x42
    IiDisp8EVEX FV32
    IiDisp8MVEX Us32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W0
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0, MVEX.512.66.0F38.W0
    RET
  ENDP IizVGETEXPPS::
↑ VGETEXPPD
Convert Exponents of Packed DP FP Values to DP FP Values
Intel reference
VGETEXPPD xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F38.W1 42 /r
VGETEXPPD ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F38.W1 42 /r
VGETEXPPD zmm1 {k1}{z}, zmm2/m512/m64bcst{sae} EVEX.512.66.0F38.W1 42 /r
VGETEXPPD zmm1 {k1}, zmm2/m512/m64bcst{sae} MVEX.512.66.0F38.W1 42 /r
Opcode
0x42
Tested by
t5460 
IizVGETEXPPD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiAllowSuppressing
    IiEncoding DATA=QWORD
    IiDisp8EVEX FV64
    IiDisp8MVEX Ub64
    IiOpEn RM
    IiModRM /r
    IiEmitOpcode 0x42
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W1, MVEX.512.66.0F38.W1
    RET
  ENDP IizVGETEXPPD::
↑ VGETMANTSS
Extract Float32 Vector of Normalized Mantissa from Float32 Vector
Intel reference
VGETMANTSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}, imm8 EVEX.NDS.LIG.66.0F3A.W0 27 /r ib
Opcode
0x27
Tested by
t5462 
IizVGETMANTSS:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Operand=DH,Register=xmm
    IiEmitOpcode 0x27
    IiDisp8EVEX T1S32
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE, Max=15
    IiEmitPrefix EVEX.NDS.LIG.66.0F3A.W0
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVGETMANTSS::
↑ VGETMANTSD
Extract Float64 of Normalized Mantissas from Float64 Scalar
Intel reference
VGETMANTSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8 EVEX.NDS.LIG.66.0F3A.W1 27 /r ib
Opcode
0x27
Tested by
t5462 
IizVGETMANTSD:: PROC
    IiAllowModifier MASK
    IiAllowSuppressing Operand=DH, Register=xmm
    IiEmitOpcode 0x27
    IiDisp8EVEX T1S64
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE, Max=15
    IiEmitPrefix EVEX.NDS.LIG.66.0F3A.W1
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IizVGETMANTSD::
↑ VGETMANTPS
Extract Float32 Vector of Normalized Mantissas from Float32 Vector
Intel reference
VGETMANTPS xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8 EVEX.128.66.0F3A.W0 26 /r ib
VGETMANTPS ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8 EVEX.256.66.0F3A.W0 26 /r ib
VGETMANTPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae}, imm8 EVEX.512.66.0F3A.W0 26 /r ib
VGETMANTPS zmm1 {k1}, zmm2/m512/m32bcst{sae}, imm8 MVEX.512.66.0F3A.W0 26 /r ib
Opcode
0x26
Tested by
t5462 
IizVGETMANTPS:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD, Operand=DH
    IiAllowSuppressing Operand=DH 
    IiEmitOpcode 0x26
    IiDisp8EVEX FV32
    IiDisp8MVEX Us32
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE, Max=15
    IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.mem.imm:
.xmm.xmm.imm:
    IiEmitPrefix EVEX.128.66.0F3A.W0
    RET
.ymm.mem.imm:
.ymm.ymm.imm:
    IiEmitPrefix EVEX.256.66.0F3A.W0
    RET
.zmm.mem.imm:
 .Z:IiEmitPrefix EVEX.512.66.0F3A.W0, MVEX.512.66.0F3A.W0
    RET
.zmm.zmm.imm:
    JMP .Z:
  ENDP IizVGETMANTPS::
↑ VGETMANTPD
Extract Float64 Vector of Normalized Mantissas from Float64 Vector
Intel reference
VGETMANTPD xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8 EVEX.128.66.0F3A.W1 26 /r ib
VGETMANTPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8 EVEX.256.66.0F3A.W1 26 /r ib
VGETMANTPD zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}, imm8 EVEX.512.66.0F3A.W1 26 /r ib
VGETMANTPD zmm1 {k1}, zmm2/m512/m64bcst{sae}, imm8 MVEX.512.66.0F3A.W1 26 /r ib
Opcode
0x26
Tested by
t5462 
IizVGETMANTPD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD, Operand=DH
    IiAllowSuppressing Operand=DH
    IiEmitOpcode 0x26
    IiDisp8EVEX FV64
    IiDisp8MVEX Ub64
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE, Max=15
    IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.mem.imm:
.xmm.xmm.imm:
    IiEmitPrefix EVEX.128.66.0F3A.W1
    RET
.ymm.mem.imm:
.ymm.ymm.imm:
    IiEmitPrefix EVEX.256.66.0F3A.W1
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.512.66.0F3A.W1, MVEX.512.66.0F3A.W1
    RET
  ENDP IizVGETMANTPD::
↑ VMOVD
Move Doubleword
Intel reference
VMOVD xmm1, r32/m32 VEX.128.66.0F.W0 6E /r
VMOVD xmm1, r32/m32 EVEX.128.66.0F.W0 6E /r
VMOVD r32/m32, xmm1 VEX.128.66.0F.W0 7E /r
VMOVD r32/m32, xmm1 EVEX.128.66.0F.W0 7E /r
Category
mmx,datamov
Operands
Pq,Ed | Pq,Ed | Vdq,Ed | Vdq,Ed | Ed,Pq | Ed,Pq | Ed,Vdq | Ed,Vdq
Opcode
0x0F6E /r | 0x0F6E /r | 0x660F6E /r | 0x660F6E /r | 0x0F7E /r | 0x0F7E /r | 0x660F7E /r | 0x660F7E /r
CPU
PX+
Tested by
t5470 
IizVMOVD:: PROC
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.128.66.0F.W0, EVEX.128.66.0F.W0
    IiDisp8EVEX T1S32
    IiModRM /r
    IiDispatchFormat  xmm.r32, xmm.mem, r32.xmm, mem.xmm
.xmm.r32:
.xmm.mem:
    IiEmitOpcode 0x6E
    IiOpEn RM
    RET
.r32.xmm:
.mem.xmm:
    IiEmitOpcode 0x7E
    IiOpEn MR
    RET
  ENDP IizVMOVD::
↑ VMOVQ
Move Quadword
Intel reference
VMOVQ xmm1, r64/m64 VEX.128.66.0F.W1 6E /r
VMOVQ xmm1, r64/m64 EVEX.128.66.0F.W1 6E /r
VMOVQ r64/m64, xmm1 VEX.128.66.0F.W1 7E /r
VMOVQ r64/m64, xmm1 EVEX.128.66.0F.W1 7E /r
VMOVQ xmm1, xmm2/m64 VEX.128.F3.0F.WIG 7E /r
VMOVQ xmm1, xmm2/m64 EVEX.128.F3.0F.W1 7E /r
VMOVQ xmm1/m64, xmm2 VEX.128.66.0F.WIG D6 /r
VMOVQ xmm1/m64, xmm2 EVEX.128.66.0F.W1 D6 /r
Category
mmx,datamov
Operands
Pq,Eqp | Vdq,Eqp | Eqp,Pq | Eqp,Edq | Pq,Qq | Vq,Wq | Qq,Pq | Wq,Vq
Opcode
0x0F6E /r | 0x660F6E /r | 0x0F7E /r | 0x660F7E /r | 0x0F6F /r | 0xF30F7E /r | 0x0F7F /r | 0x660FD6 /r
CPU
P4+
Documented
D31
Tested by
t5470 
IizVMOVQ:: PROC
    IiAllowModifier CODE
    IiDisp8EVEX T1S64
    IiModRM /r
    IiDispatchFormat  xmm.r64, xmm.mem, r64.xmm, mem.xmm, xmm.xmm
.xmm.r64:
    IiEncoding DATA=QWORD,CODE=SHORT
    IiEmitPrefix VEX.128.66.0F.W1, EVEX.128.66.0F.W1
    IiEmitOpcode 0x6E
    IiOpEn RM
    RET
.r64.xmm:
    IiEncoding DATA=QWORD,CODE=LONG
    IiEmitPrefix VEX.128.66.0F.W1, EVEX.128.66.0F.W1
    IiEmitOpcode 0x7E
    IiOpEn MR
    RET
.xmm.mem:
    JNSt [EDI+II.SssStatus],sssWidth64, .xmm.mem.L:
    IiDispatchCode SHORT=.xmm.r64:
.xmm.mem.L:
    IiEncoding DATA=QWORD,CODE=LONG
    IiEmitPrefix VEX.128.F3.0F.WIG, EVEX.128.F3.0F.W1
    IiEmitOpcode 0x7E
    IiOpEn RM
    RET
.xmm.xmm:
    IiDispatchCode LONG=.xmm.mem.L:
.xmm.xmm.S:
    IiEncoding DATA=QWORD,CODE=SHORT
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
    IiEmitOpcode 0xD6
    IiOpEn MR
    RET
.mem.xmm:
    JNSt [EDI+II.SssStatus],sssWidth64,.xmm.xmm.S:
    IiDispatchCode LONG=.r64.xmm:
    JMP .xmm.xmm.S:
  ENDP IizVMOVQ::
↑ VMOVSS
Move or Merge Scalar Single-Precision Floating-Point Value
Intel reference
VMOVSS xmm1, xmm2, xmm3 VEX.NDS.LIG.F3.0F.WIG 10 /r
VMOVSS xmm1, m32 VEX.LIG.F3.0F.WIG 10 /r
VMOVSS xmm1, xmm2, xmm3 VEX.NDS.LIG.F3.0F.WIG 11 /r
VMOVSS m32, xmm1 VEX.LIG.F3.0F.WIG 11 /r
VMOVSS xmm1 {k1}{z}, xmm2, xmm3 EVEX.NDS.LIG.F3.0F.W0 10 /r
VMOVSS xmm1 {k1}{z}, m32 EVEX.LIG.F3.0F.W0 10 /r
VMOVSS xmm1 {k1}{z}, xmm2, xmm3 EVEX.NDS.LIG.F3.0F.W0 11 /r
VMOVSS m32 {k1}, xmm1 EVEX.LIG.F3.0F.W0 11 /r
Category
sse1,simdfp,datamov
Operands
Vss,Wss | Wss,Vss
Opcode
0xF30F10 /r | 0xF30F11 /r
CPU
P3+
Tested by
t5472 
IizVMOVSS:: PROC
    IiAllowModifier MASK,CODE
    IiEmitPrefix VEX.LIG.F3.0F.WIG, EVEX.LIG.F3.0F.W0
    IiDisp8EVEX T1S32
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.mem, mem.xmm
.xmm.mem:
    IiOpEn RM 
 .S:IiEncoding DATA=DWORD,CODE=SHORT
    IiEmitOpcode 0x10
    RET
.mem.xmm:
    IiOpEn MR
 .L:IiEncoding DATA=DWORD,CODE=LONG
    IiEmitOpcode 0x11    
    RET
.xmm.xmm.xmm:
    IiDispatchCode LONG=.MVR:
    IiOpEn RVM
    JMP .S:
.MVR:IiOpEn MVR
    JMP .L:
  ENDP IizVMOVSS::
↑ VMOVSD
Move or Merge Scalar Double-Precision Floating-Point Value
Intel reference
VMOVSD xmm1, xmm2, xmm3 VEX.NDS.LIG.F2.0F.WIG 10 /r
VMOVSD xmm1, m64 VEX.LIG.F2.0F.WIG 10 /r
VMOVSD xmm1, xmm2, xmm3 VEX.NDS.LIG.F2.0F.WIG 11 /r
VMOVSD m64, xmm1 VEX.LIG.F2.0F.WIG 11 /r
VMOVSD xmm1 {k1}{z}, xmm2, xmm3 EVEX.NDS.LIG.F2.0F.W1 10 /r
VMOVSD xmm1 {k1}{z}, m64 EVEX.LIG.F2.0F.W1 10 /r
VMOVSD xmm1 {k1}{z}, xmm2, xmm3 EVEX.NDS.LIG.F2.0F.W1 11 /r
VMOVSD m64 {k1}, xmm1 EVEX.LIG.F2.0F.W1 11 /r
Category
gen,datamov string
Operands
Ydo,Xdo | Ydo,Xdo | Vsd,Wsd | Wsd,Vsd
Opcode
0xA5 ^W | 0xA5 ^W | 0xF20F10 /r | 0xF20F11 /r
Flags
tested:.D......
CPU
03+
Tested by
t5472 
IizVMOVSD:: PROC
    IiAllowModifier MASK,CODE
    IiEmitPrefix VEX.LIG.F2.0F.WIG, EVEX.LIG.F2.0F.W1
    IiDisp8EVEX T1S64
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.mem, mem.xmm
.xmm.mem:
    IiOpEn RM
 .S:IiEncoding DATA=QWORD,CODE=SHORT
    IiEmitOpcode 0x10    
    RET
.mem.xmm:
    IiOpEn MR
 .L:IiEncoding DATA=QWORD,CODE=LONG
    IiEmitOpcode 0x11
    RET
.xmm.xmm.xmm:
    IiOpEn MVR
    JSt [EDI+II.MfgExplicit],iiMfgCODE_LONG, .L:
    IiOpEn RVM
    JMP .S:
  ENDP IizVMOVSD::
↑ VMOVUPS
Move Unaligned Packed Single-FP Values
Intel reference
VMOVUPS xmm1, xmm2/m128 VEX.128.0F.WIG 10 /r
VMOVUPS xmm2/m128, xmm1 VEX.128.0F.WIG 11 /r
VMOVUPS ymm1, ymm2/m256 VEX.256.0F.WIG 10 /r
VMOVUPS ymm2/m256, ymm1 VEX.256.0F.WIG 11 /r
VMOVUPS xmm1 {k1}{z}, xmm2/m128 EVEX.128.0F.W0 10 /r
VMOVUPS ymm1 {k1}{z}, ymm2/m256 EVEX.256.0F.W0 10 /r
VMOVUPS zmm1 {k1}{z}, zmm2/m512 EVEX.512.0F.W0 10 /r
VMOVUPS xmm2/m128 {k1}{z}, xmm1 EVEX.128.0F.W0 11 /r
VMOVUPS ymm2/m256 {k1}{z}, ymm1 EVEX.256.0F.W0 11 /r
VMOVUPS zmm2/m512 {k1}{z}, zmm1 EVEX.512.0F.W0 11 /r
Category
sse1,simdfp,datamov
Operands
Vps,Wps | Wps,Vps
Opcode
0x0F10 /r | 0x0F11 /r
CPU
P3+
Tested by
t5478 
IizVMOVUPS:: PROC
    IiAllowModifier MASK,CODE
    IiModRM /r
    IiDisp8EVEX FV32
    IiDispatchFormat  xmm.xmm, xmm.mem, mem.xmm, ymm.ymm, ymm.mem, mem.ymm, zmm.zmm, zmm.mem, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
 .S:IiEncoding DATA=DWORD,CODE=SHORT
    IiEmitOpcode 0x10
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
 .L:IiEncoding DATA=DWORD,CODE=LONG
    IiEmitOpcode 0x11
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode  LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.0F.WIG, EVEX.256.0F.W0
    JMP .S:
.mem.ymm:
    IiEmitPrefix VEX.256.0F.WIG, EVEX.256.0F.W0
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.0F.W0
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.0F.W0
    JMP .L:
  ENDP IizVMOVUPS::
↑ VMOVUPD
Move Unaligned Packed Double-FP Value
Intel reference
VMOVUPD xmm1, xmm2/m128 VEX.128.66.0F.WIG 10 /r
VMOVUPD xmm2/m128, xmm1 VEX.128.66.0F.WIG 11 /r
VMOVUPD ymm1, ymm2/m256 VEX.256.66.0F.WIG 10 /r
VMOVUPD ymm2/m256, ymm1 VEX.256.66.0F.WIG 11 /r
VMOVUPD xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F.W1 10 /r
VMOVUPD xmm2/m128 {k1}{z}, xmm1 EVEX.128.66.0F.W1 11 /r
VMOVUPD ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F.W1 10 /r
VMOVUPD ymm2/m256 {k1}{z}, ymm1 EVEX.256.66.0F.W1 11 /r
VMOVUPD zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F.W1 10 /r
VMOVUPD zmm2/m512 {k1}{z}, zmm1 EVEX.512.66.0F.W1 11 /r
Category
sse2,pcksclr,datamov
Operands
Vpd,Wpd | Wpd,Vpd
Opcode
0x660F10 /r | 0x660F11 /r
CPU
P4+
Tested by
t5478 
IizVMOVUPD:: PROC
    IiAllowModifier MASK,CODE
    IiModRM /r
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm, xmm.mem, mem.xmm, ymm.ymm, ymm.mem, mem.ymm, zmm.zmm, zmm.mem, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
 .S:IiEncoding DATA=DWORD,CODE=SHORT
    IiEmitOpcode 0x10
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
 .L:IiEncoding DATA=DWORD,CODE=LONG
    IiEmitOpcode 0x11
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W1
    JMP .S:
.mem.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W1
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F.W1
    JMP .L:
  ENDP IizVMOVUPD::
↑ VMOVAPS
Move Aligned Packed Single-Precision Floating-Point Values
Intel reference
VMOVAPS xmm1, xmm2/m128 VEX.128.0F.WIG 28 /r
VMOVAPS xmm2/m128, xmm1 VEX.128.0F.WIG 29 /r
VMOVAPS ymm1, ymm2/m256 VEX.256.0F.WIG 28 /r
VMOVAPS ymm2/m256, ymm1 VEX.256.0F.WIG 29 /r
VMOVAPS xmm1 {k1}{z}, xmm2/m128 EVEX.128.0F.W0 28 /r
VMOVAPS ymm1 {k1}{z}, ymm2/m256 EVEX.256.0F.W0 28 /r
VMOVAPS zmm1 {k1}{z}, zmm2/m512 EVEX.512.0F.W0 28 /r
VMOVAPS xmm2/m128 {k1}{z}, xmm1 EVEX.128.0F.W0 29 /r
VMOVAPS ymm2/m256 {k1}{z}, ymm1 EVEX.256.0F.W0 29 /r
VMOVAPS zmm2/m512 {k1}{z}, zmm1 EVEX.512.0F.W0 29 /r
VMOVAPS zmm1 {k1}, zmm2/mem MVEX.512.0F.W0 28 /r
VMOVAPS zmm2/mem {k1}, zmm1 MVEX.512.0F.W0 29 /r
Opcode
0x28 || 0x29
Tested by
t5476 
IizVMOVAPS:: PROC
    IiAllowModifier MASK,CODE
    IiDisp8EVEX FVM
    IiDisp8MVEX Dn32
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, mem.xmm, ymm.ymm, ymm.mem, mem.ymm, zmm.zmm, zmm.mem, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
 .S:IiEncoding DATA=DWORD,CODE=SHORT
    IiEmitOpcode 0x28
    IiOpEn RM
    RET
.mem.xmm:    
    IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
 .L:IiEncoding DATA=DWORD,CODE=LONG
    IiEmitOpcode 0x29
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.0F.WIG, EVEX.256.0F.W0
    JMP .S:
.mem.ymm:
    IiEmitPrefix VEX.256.0F.WIG, EVEX.256.0F.W0
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.0F.W0, MVEX.512.0F.W0
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.0F.W0, MVEX.512.0F.W0
    JMP .L:
  ENDP IizVMOVAPS::
↑ VMOVAPD
Move Aligned Packed Double-Precision Floating-Point Values
Intel reference
VMOVAPD xmm1, xmm2/m128 VEX.128.66.0F.WIG 28 /r
VMOVAPD xmm2/m128, xmm1 VEX.128.66.0F.WIG 29 /r
VMOVAPD ymm1, ymm2/m256 VEX.256.66.0F.WIG 28 /r
VMOVAPD ymm2/m256, ymm1 VEX.256.66.0F.WIG 29 /r
VMOVAPD xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F.W1 28 /r
VMOVAPD ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F.W1 28 /r
VMOVAPD zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F.W1 28 /r
VMOVAPD xmm2/m128 {k1}{z}, xmm1 EVEX.128.66.0F.W1 29 /r
VMOVAPD ymm2/m256 {k1}{z}, ymm1 EVEX.256.66.0F.W1 29 /r
VMOVAPD zmm2/m512 {k1}{z}, zmm1 EVEX.512.66.0F.W1 29 /r
VMOVAPD zmm1 {k1}{z}, zmm2/m512 MVEX.512.66.0F.W1 28 /r
VMOVAPD zmm2/m512 {k1}{z}, zmm1 MVEX.512.66.0F.W1 29 /r
Opcode
0x28 || 0x29
Tested by
t5476 
IizVMOVAPD:: PROC
    IiAllowModifier MASK, CODE
    IiDisp8EVEX FVM
    IiDisp8MVEX Di64
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, mem.xmm, ymm.ymm, ymm.mem, mem.ymm, zmm.zmm, zmm.mem, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
 .S:IiEncoding DATA=QWORD,CODE=SHORT
    IiEmitOpcode 0x28
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
 .L:IiEncoding DATA=QWORD,CODE=LONG
    IiEmitOpcode 0x29
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W1
    JMP .S:
.mem.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W1
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1, MVEX.512.66.0F.W1
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F.W1, MVEX.512.66.0F.W1
    JMP .L:
  ENDP IizVMOVAPD::
↑ VMOVLPS
Move Low Packed Single-FP Values
Intel reference
VMOVLPS xmm2, xmm1, m64 VEX.NDS.128.0F.WIG 12 /r
VMOVLPS xmm2, xmm1, m64 EVEX.NDS.128.0F.W0 12 /r
VMOVLPS m64, xmm1 VEX.128.0F.WIG 13/r
VMOVLPS m64, xmm1 EVEX.128.0F.W0 13/r
Category
sse1,simdfp,datamov
Operands
Vq,Mq | Mq,Vq
Opcode
0x0F12 /r | 0x0F13 /r
CPU
P3+
Tested by
t5480 
IizVMOVLPS:: PROC
    MOV AL,0x12
    MOV CL,0x13
.op:IiDisp8EVEX T1S64
    IiModRM /r
    IiEncoding DATA=DWORD
    IiDispatchFormat  xmm.xmm.mem, mem.xmm
.xmm.xmm.mem:
    IiEmitOpcode EAX
    IiEmitPrefix VEX.NDS.128.0F.WIG, EVEX.NDS.128.0F.W0
    IiOpEn RVM
    RET
.mem.xmm:
    IiEmitOpcode ECX
    IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
    IiOpEn MR
    RET
  ENDP IizVMOVLPS::
↑ VMOVHPS
Move High Packed Single-FP Values
Intel reference
VMOVHPS xmm2, xmm1, m64 VEX.NDS.128.0F.WIG 16 /r
VMOVHPS xmm2, xmm1, m64 EVEX.NDS.128.0F.W0 16 /r
VMOVHPS m64, xmm1 VEX.128.0F.WIG 17 /r
VMOVHPS m64, xmm1 EVEX.128.0F.W0 17 /r
Category
sse1,simdfp,datamov
Operands
Vq,Mq | Mq,Vq
Opcode
0x0F16 /r | 0x0F17 /r
CPU
P3+
Tested by
t5480 
IizVMOVHPS:: PROC
    MOV AL,0x16
    MOV CL,0x17
    JMP IizVMOVLPS.op:
  ENDP IizVMOVHPS::
↑ VMOVLPD
Move Low Packed Double-FP Value
Intel reference
VMOVLPD xmm2, xmm1, m64 VEX.NDS.128.66.0F.WIG 12 /r
VMOVLPD xmm2, xmm1, m64 EVEX.NDS.128.66.0F.W1 12 /r
VMOVLPD m64, xmm1 VEX.128.66.0F.WIG 13/r
VMOVLPD m64, xmm1 EVEX.128.66.0F.W1 13/r
Category
sse2,pcksclr,datamov
Operands
Vq,Mq | Mq,Vq
Opcode
0x660F12 /r | 0x660F13 /r
CPU
P4+
Tested by
t5480 
IizVMOVLPD:: PROC
    MOV AL,0x12
    MOV CL,0x13
.op:IiDisp8EVEX T1S64
    IiModRM /r
    IiEncoding DATA=QWORD
    IiDispatchFormat  xmm.xmm.mem, mem.xmm
.xmm.xmm.mem:
    IiEmitOpcode EAX
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W1
    IiOpEn RVM
    RET
.mem.xmm:
    IiEmitOpcode ECX
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
    IiOpEn MR
    RET
  ENDP IizVMOVLPD::
↑ VMOVHPD
Move High Packed Double-FP Value
Intel reference
VMOVHPD xmm2, xmm1, m64 VEX.NDS.128.66.0F.WIG 16 /r
VMOVHPD xmm2, xmm1, m64 EVEX.NDS.128.66.0F.W1 16 /r
VMOVHPD m64, xmm1 VEX.128.66.0F.WIG 17 /r
VMOVHPD m64, xmm1 EVEX.128.66.0F.W1 17 /r
Category
sse2,pcksclr,datamov
Operands
Vq,Mq | Mq,Vq
Opcode
0x660F16 /r | 0x660F17 /r
CPU
P4+
Tested by
t5480 
IizVMOVHPD:: PROC
    MOV AL,0x16
    MOV CL,0x17
    JMP IizVMOVLPD.op:
  ENDP IizVMOVHPD::
↑ VMOVLHPS
Move Packed Single-FP Values Low to High
Intel reference
VMOVLHPS xmm1, xmm2, xmm3 VEX.NDS.128.0F.WIG 16 /r
VMOVLHPS xmm1, xmm2, xmm3 EVEX.NDS.128.0F.W0 16 /r
Category
sse1,simdfp,datamov
Operands
Vq,Uq
Opcode
0x0F16 /r
CPU
P3+
Tested by
t5480 
IizVMOVLHPS:: PROC
    IiEmitOpcode 0x16
.op:IiOpEn RVM
    IiEmitPrefix VEX.NDS.128.0F.WIG, EVEX.NDS.128.0F.W0
    IiModRM /r
    IiEncoding DATA=DWORD
    IiDispatchFormat  xmm.xmm.xmm
.xmm.xmm.xmm:
    RET
  ENDP IizVMOVLHPS::
↑ VMOVHLPS
Move Packed Single-FP Values High to Low
Intel reference
VMOVHLPS xmm1, xmm2, xmm3 VEX.NDS.128.0F.WIG 12 /r
VMOVHLPS xmm1, xmm2, xmm3 EVEX.NDS.128.0F.W0 12 /r
Category
sse1,simdfp,datamov
Operands
Vq,Uq
Opcode
0x0F12 /r
CPU
P3+
Tested by
t5480 
IizVMOVHLPS:: PROC
    IiEmitOpcode 0x12
    JMP IizVMOVLHPS.op:
  ENDP IizVMOVHLPS::
↑ VMOVSLDUP
Move Packed Single-FP Low and Duplicate
Intel reference
VMOVSLDUP xmm1, xmm2/m128 VEX.128.F3.0F.WIG 12 /r
VMOVSLDUP ymm1, ymm2/m256 VEX.256.F3.0F.WIG 12 /r
VMOVSLDUP xmm1 {k1}{z}, xmm2/m128 EVEX.128.F3.0F.W0 12 /r
VMOVSLDUP ymm1 {k1}{z}, ymm2/m256 EVEX.256.F3.0F.W0 12 /r
VMOVSLDUP zmm1 {k1}{z}, zmm2/m512 EVEX.512.F3.0F.W0 12 /r
Category
sse3,simdfp,datamov
Operands
Vq,Wq
Opcode
0xF30F12 /r
CPU
P4++
Tested by
t5482 
IizVMOVSLDUP:: PROC
    IiEmitOpcode 0x12
.op:IiAllowModifier MASK
    IiDisp8EVEX FV32
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
    IiEmitPrefix VEX.128.F3.0F.WIG, EVEX.128.F3.0F.W0
    RET
.ymm.mem:
.ymm.ymm:
    IiEmitPrefix VEX.256.F3.0F.WIG, EVEX.256.F3.0F.W0
    RET
.zmm.mem:
.zmm.zmm:
    IiEmitPrefix EVEX.512.F3.0F.W0
    RET
  ENDP IizVMOVSLDUP::
↑ VMOVSHDUP
Move Packed Single-FP High and Duplicate
Intel reference
VMOVSHDUP xmm1, xmm2/m128 VEX.128.F3.0F.WIG 16 /r
VMOVSHDUP ymm1, ymm2/m256 VEX.256.F3.0F.WIG 16 /r
VMOVSHDUP xmm1 {k1}{z}, xmm2/m128 EVEX.128.F3.0F.W0 16 /r
VMOVSHDUP ymm1 {k1}{z}, ymm2/m256 EVEX.256.F3.0F.W0 16 /r
VMOVSHDUP zmm1 {k1}{z}, zmm2/m512 EVEX.512.F3.0F.W0 16 /r
Category
sse3,simdfp,datamov
Operands
Vq,Wq
Opcode
0xF30F16 /r
CPU
P4++
Tested by
t5482 
IizVMOVSHDUP:: PROC
    IiEmitOpcode 0x16
    JMP IizVMOVSLDUP.op:
  ENDP IizVMOVSHDUP::
↑ VMOVDQA
Move Aligned Double Quadword
Intel reference
VMOVDQA xmm1, xmm2/m128 VEX.128.66.0F.WIG 6F /r
VMOVDQA xmm2/m128, xmm1 VEX.128.66.0F.WIG 7F /r
VMOVDQA ymm1, ymm2/m256 VEX.256.66.0F.WIG 6F /r
VMOVDQA ymm2/m256, ymm1 VEX.256.66.0F.WIG 7F /r
Category
sse2,simdint,datamov
Operands
Vdq,Wdq | Wdq,Vdq
Opcode
0x660F6F /r | 0x660F7F /r
CPU
P4+
Tested by
t5484 
IizVMOVDQA:: PROC
    IiAllowModifier MASK,CODE
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, mem.xmm, ymm.ymm, ymm.mem, mem.ymm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F.WIG
 .S:IiEncoding CODE=SHORT
    IiEmitOpcode 0x6F
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG
 .L:IiEncoding CODE=LONG
    IiEmitOpcode 0x7F
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F.WIG
    JMP .S:
.mem.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG
    JMP .L:
  ENDP IizVMOVDQA::
↑ VMOVQQA
Move Aligned Double Quadword
Comment
Alias to VMOVDQA for better compatibility with NASM.
Intel reference
VMOVQQA xmm1, xmm2/m128 VEX.128.66.0F.WIG 6F /r
VMOVQQA xmm2/m128, xmm1 VEX.128.66.0F.WIG 7F /r
VMOVQQA ymm1, ymm2/m256 VEX.256.66.0F.WIG 6F /r
VMOVQQA ymm2/m256, ymm1 VEX.256.66.0F.WIG 7F /r
Category
sse2,simdint,datamov
Operands
Vdq,Wdq | Wdq,Vdq
Opcode
0x660F6F /r | 0x660F7F /r
CPU
P4+
Tested by
t5484 
IizVMOVQQA:: PROC
    JMP IizVMOVDQA:
  ENDP IizVMOVQQA::
↑ VMOVDQA32
Move Aligned Packed DWORD Integer Values
Intel reference
VMOVDQA32 xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F.W0 6F /r
VMOVDQA32 ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F.W0 6F /r
VMOVDQA32 zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F.W0 6F /r
VMOVDQA32 xmm2/m128 {k1}{z}, xmm1 EVEX.128.66.0F.W0 7F /r
VMOVDQA32 ymm2/m256 {k1}{z}, ymm1 EVEX.256.66.0F.W0 7F /r
VMOVDQA32 zmm2/m512 {k1}{z}, zmm1 EVEX.512.66.0F.W0 7F /r
VMOVDQA32 zmm1 {k1}, zmm2/mem MVEX.512.66.0F.W0 6F /r
VMOVDQA32 zmm1/mem {k1}, zmm2 MVEX.512.66.0F.W0 7F /r
Opcode
0x6F | 0x7F
Tested by
t5484 
IizVMOVDQA32:: PROC
    IiAllowModifier MASK,CODE
    IiDisp8EVEX FV32
    IiDisp8MVEX Un32
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem, mem.xmm, mem.ymm, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W0
 .S:IiEncoding DATA=DWORD,CODE=SHORT
    IiEmitOpcode 0x6F     
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F.W0
 .L:IiEncoding DATA=DWORD,CODE=LONG
    IiEmitOpcode 0x7F     
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W0
    JMP .S:
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F.W0
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W0, MVEX.512.66.0F.W0
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F.W0, MVEX.512.66.0F.W0
    JMP .L:
  ENDP IizVMOVDQA32::
↑ VMOVDQA64
Move Aligned Packed QWORD Integer Values
Intel reference
VMOVDQA64 xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F.W1 6F /r
VMOVDQA64 ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F.W1 6F /r
VMOVDQA64 zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F.W1 6F /r
VMOVDQA64 xmm2/m128 {k1}{z}, xmm1 EVEX.128.66.0F.W1 7F /r
VMOVDQA64 ymm2/m256 {k1}{z}, ymm1 EVEX.256.66.0F.W1 7F /r
VMOVDQA64 zmm2/m512 {k1}{z}, zmm1 EVEX.512.66.0F.W1 7F /r
VMOVDQA64 zmm1 {k1}, zmm2/m512 MVEX.512.66.0F.W1 6F /r
VMOVDQA64 zmm1/m512 {k1}, zmm2 MVEX.512.66.0F.W1 7F /r
Opcode
0x6F | 0x7F
Tested by
t5484 
IizVMOVDQA64:: PROC
    IiAllowModifier MASK,CODE
    IiDisp8EVEX FV64
    IiDisp8MVEX Di64
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem, mem.xmm, mem.ymm, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F.W1
 .S:IiEncoding DATA=QWORD,CODE=SHORT
    IiEmitOpcode 0x6F     
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix EVEX.128.66.0F.W1
 .L:IiEncoding DATA=QWORD,CODE=LONG
    IiEmitOpcode 0x7F     
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F.W1
    JMP .S:
.mem.ymm:
    IiEmitPrefix EVEX.256.66.0F.W1
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F.W1, MVEX.512.66.0F.W1
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F.W1, MVEX.512.66.0F.W1
    JMP .L:
  ENDP IizVMOVDQA64::
↑ VMOVDQU
Move Unaligned Double Quadword
Intel reference
VMOVDQU xmm1, xmm2/m128 VEX.128.F3.0F.WIG 6F /r
VMOVDQU xmm2/m128, xmm1 VEX.128.F3.0F.WIG 7F /r
VMOVDQU ymm1, ymm2/m256 VEX.256.F3.0F.WIG 6F /r
VMOVDQU ymm2/m256, ymm1 VEX.256.F3.0F.WIG 7F /r
Category
sse2,simdint,datamov
Operands
Vdq,Wdq | Wdq,Vdq
Opcode
0xF30F6F /r | 0xF30F7F /r
CPU
P4+
Tested by
t5486 
IizVMOVDQU:: PROC
    IiAllowModifier CODE
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, mem.xmm, ymm.ymm, ymm.mem, mem.ymm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.F3.0F.WIG
 .S:IiEncoding CODE=SHORT
    IiEmitOpcode 0x6F
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix VEX.128.F3.0F.WIG
 .L:IiEncoding CODE=LONG
    IiEmitOpcode 0x7F
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.F3.0F.WIG
    JMP .S:
.mem.ymm:
    IiEmitPrefix VEX.256.F3.0F.WIG
    JMP .L:
  ENDP IizVMOVDQU::
↑ VMOVQQU
Move Unaligned Double Quadword
Comment
Alias to VMOVDQU for better compatibility with NASM.
Intel reference
VMOVQQU xmm1, xmm2/m128 VEX.128.F3.0F.WIG 6F /r
VMOVQQU xmm2/m128, xmm1 VEX.128.F3.0F.WIG 7F /r
VMOVQQU ymm1, ymm2/m256 VEX.256.F3.0F.WIG 6F /r
VMOVQQU ymm2/m256, ymm1 VEX.256.F3.0F.WIG 7F /r
Category
sse2,simdint,datamov
Operands
Vdq,Wdq | Wdq,Vdq
Opcode
0xF30F6F /r | 0xF30F7F /r
CPU
P4+
Tested by
t5486 
IizVMOVQQU:: PROC
    JMP IizVMOVDQU:
  ENDP IizVMOVQQU::
↑ VMOVDQU8
Move Unaligned Packed BYTE Integer Values
Intel reference
VMOVDQU8 xmm1 {k1}{z}, xmm2/m128 EVEX.128.F2.0F.W0 6F /r
VMOVDQU8 ymm1 {k1}{z}, ymm2/m256 EVEX.256.F2.0F.W0 6F /r
VMOVDQU8 zmm1 {k1}{z}, zmm2/m512 EVEX.512.F2.0F.W0 6F /r
VMOVDQU8 xmm2/m128 {k1}{z}, xmm1 EVEX.128.F2.0F.W0 7F /r
VMOVDQU8 ymm2/m256 {k1}{z}, ymm1 EVEX.256.F2.0F.W0 7F /r
VMOVDQU8 zmm2/m512 {k1}{z}, zmm1 EVEX.512.F2.0F.W0 7F /r
Opcode
0x6F | 0x7F
Tested by
t5486 
IizVMOVDQU8:: PROC
    IiAllowModifier MASK,CODE
    IiDisp8EVEX FVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem, mem.xmm, mem.ymm, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.F2.0F.W0
 .S:IiEncoding DATA=BYTE,CODE=SHORT
    IiEmitOpcode 0x6F
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix EVEX.128.F2.0F.W0
 .L:IiEncoding DATA=BYTE,CODE=LONG
    IiEmitOpcode 0x7F
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.F2.0F.W0
    JMP .S:
.mem.ymm:
    IiEmitPrefix EVEX.256.F2.0F.W0
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F2.0F.W0
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.F2.0F.W0
    JMP .L:
  ENDP IizVMOVDQU8::
↑ VMOVDQU16
Move Unaligned Packed WORD Integer Value
Intel reference
VMOVDQU16 xmm1 {k1}{z}, xmm2/m128 EVEX.128.F2.0F.W1 6F /r
VMOVDQU16 ymm1 {k1}{z}, ymm2/m256 EVEX.256.F2.0F.W1 6F /r
VMOVDQU16 zmm1 {k1}{z}, zmm2/m512 EVEX.512.F2.0F.W1 6F /r
VMOVDQU16 xmm2/m128 {k1}{z}, xmm1 EVEX.128.F2.0F.W1 7F /r
VMOVDQU16 ymm2/m256 {k1}{z}, ymm1 EVEX.256.F2.0F.W1 7F /r
VMOVDQU16 zmm2/m512 {k1}{z}, zmm1 EVEX.512.F2.0F.W1 7F /r
Opcode
0x6F | 0x7F
Tested by
t5486 
IizVMOVDQU16:: PROC
  IiAllowModifier MASK,CODE
    IiDisp8EVEX FVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem, mem.xmm, mem.ymm, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.F2.0F.W1
 .S:IiEncoding DATA=BYTE,CODE=SHORT
    IiEmitOpcode 0x6F
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix EVEX.128.F2.0F.W1
 .L:IiEncoding DATA=BYTE,CODE=LONG
    IiEmitOpcode 0x7F
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.F2.0F.W1
    JMP .S:
.mem.ymm:
    IiEmitPrefix EVEX.256.F2.0F.W1
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F2.0F.W1
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.F2.0F.W1
    JMP .L:
  ENDP IizVMOVDQU16::
↑ VMOVDQU32
Move Unaligned Packed DWORD Integer Values
Intel reference
VMOVDQU32 xmm1 {k1}{z}, xmm2/m128 EVEX.128.F3.0F.W0 6F /r
VMOVDQU32 ymm1 {k1}{z}, ymm2/m256 EVEX.256.F3.0F.W0 6F /r
VMOVDQU32 zmm1 {k1}{z}, zmm2/m512 EVEX.512.F3.0F.W0 6F /r
VMOVDQU32 xmm2/m128 {k1}{z}, xmm1 EVEX.128.F3.0F.W0 7F /r
VMOVDQU32 ymm2/m256 {k1}{z}, ymm1 EVEX.256.F3.0F.W0 7F /r
VMOVDQU32 zmm2/m512 {k1}{z}, zmm1 EVEX.512.F3.0F.W0 7F /r
Opcode
0x6F | 0x7F
Tested by
t5486 
IizVMOVDQU32:: PROC
  IiAllowModifier MASK,CODE
    IiDisp8EVEX FVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem, mem.xmm, mem.ymm, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.F3.0F.W0
 .S:IiEncoding DATA=BYTE,CODE=SHORT
    IiEmitOpcode 0x6F
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix EVEX.128.F3.0F.W0
 .L:IiEncoding DATA=BYTE,CODE=LONG
    IiEmitOpcode 0x7F
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.F3.0F.W0
    JMP .S:
.mem.ymm:
    IiEmitPrefix EVEX.256.F3.0F.W0
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F3.0F.W0
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.F3.0F.W0
    JMP .L:
   ENDP IizVMOVDQU32::
↑ VMOVDQU64
Move Unaligned Packed QWORD Integer Values
Intel reference
VMOVDQU64 xmm1 {k1}{z}, xmm2/m128 EVEX.128.F3.0F.W1 6F /r
VMOVDQU64 ymm1 {k1}{z}, ymm2/m256 EVEX.256.F3.0F.W1 6F /r
VMOVDQU64 zmm1 {k1}{z}, zmm2/m512 EVEX.512.F3.0F.W1 6F /r
VMOVDQU64 xmm2/m128 {k1}{z}, xmm1 EVEX.128.F3.0F.W1 7F /r
VMOVDQU64 ymm2/m256 {k1}{z}, ymm1 EVEX.256.F3.0F.W1 7F /r
VMOVDQU64 zmm2/m512 {k1}{z}, zmm1 EVEX.512.F3.0F.W1 7F /r
Opcode
0x6F | 0x7F
Tested by
t5486 
IizVMOVDQU64:: PROC
  IiAllowModifier MASK,CODE
    IiDisp8EVEX FVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem, mem.xmm, mem.ymm, mem.zmm
.xmm.xmm:
    IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.F3.0F.W1
 .S:IiEncoding DATA=BYTE,CODE=SHORT
    IiEmitOpcode 0x6F
    IiOpEn RM
    RET
.mem.xmm:
    IiEmitPrefix EVEX.128.F3.0F.W1
 .L:IiEncoding DATA=BYTE,CODE=LONG
    IiEmitOpcode 0x7F
    IiOpEn MR
    RET
.ymm.ymm:
    IiDispatchCode LONG=.mem.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.F3.0F.W1
    JMP .S:
.mem.ymm:
    IiEmitPrefix EVEX.256.F3.0F.W1
    JMP .L:
.zmm.zmm:
    IiDispatchCode LONG=.mem.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F3.0F.W1
    JMP .S:
.mem.zmm:
    IiEmitPrefix EVEX.512.F3.0F.W1
    JMP .L:
  ENDP IizVMOVDQU64::
↑ VMOVMSKPS
Extract Packed Single-FP Sign Mask
Intel reference
VMOVMSKPS reg, xmm2 VEX.128.0F.WIG 50 /r
VMOVMSKPS reg, ymm2 VEX.256.0F.WIG 50 /r
Category
sse1,simdfp,datamov
Operands
Gdqp,Ups
Opcode
0x0F50 /r
CPU
P3+
Tested by
t5490 
IizVMOVMSKPS:: PROC
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x50
    IiModRM /r
    IiOpEn RM
    IiDispatchFormat  r32.xmm, r32.ymm, r64.xmm, r64.ymm
.r64.xmm:
    IiAbortIfNot64
.r32.xmm:
    IiEmitPrefix VEX.128.0F.WIG
    RET
.r64.ymm:
    IiAbortIfNot64
.r32.ymm:
    IiEmitPrefix VEX.256.0F.WIG
    RET
  ENDP IizVMOVMSKPS::
↑ VMOVMSKPD
Extract Packed Double-FP Sign Mask
Intel reference
VMOVMSKPD reg, xmm2 VEX.128.66.0F.WIG 50 /r
VMOVMSKPD reg, ymm2 VEX.256.66.0F.WIG 50 /r
Category
sse2,pcksclr,datamov
Operands
Gdqp,Upd
Opcode
0x660F50 /r
CPU
P4+
Tested by
t5490 
IizVMOVMSKPD:: PROC
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x50
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.xmm, r32.ymm, r64.xmm, r64.ymm
.r64.xmm:
    IiAbortIfNot64
.r32.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG
    RET
.r64.ymm:
    IiAbortIfNot64
.r32.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG
    RET
  ENDP IizVMOVMSKPD::
↑ VMOVNTPS
Store Packed Single-FP Values Using Non-Temporal Hint
Intel reference
VMOVNTPS m128, xmm1 VEX.128.0F.WIG 2B /r
VMOVNTPS m256, ymm1 VEX.256.0F.WIG 2B /r
VMOVNTPS m128, xmm1 EVEX.128.0F.W0 2B /r
VMOVNTPS m256, ymm1 EVEX.256.0F.W0 2B /r
VMOVNTPS m512, zmm1 EVEX.512.0F.W0 2B /r
Category
sse1,cachect
Operands
Mps,Vps
Opcode
0x0F2B /r
CPU
P3+
Tested by
t5492 
IizVMOVNTPS:: PROC
    IiEncoding DATA=DWORD
    IiEmitOpcode 0x2B
    IiModRM /r
    IiOpEn MR
    IiDisp8EVEX FVM
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix VEX.128.0F.WIG, EVEX.128.0F.W0
    RET
.mem.ymm:
    IiEmitPrefix VEX.256.0F.WIG, EVEX.256.0F.W0
    RET
.mem.zmm:
    IiEmitPrefix EVEX.512.0F.W0
    RET
  ENDP IizVMOVNTPS::
↑ VMOVNTPD
Store Packed Double-FP Values Using Non-Temporal Hint
Intel reference
VMOVNTPD m128, xmm1 VEX.128.66.0F.WIG 2B /r
VMOVNTPD m256, ymm1 VEX.256.66.0F.WIG 2B /r
VMOVNTPD m128, xmm1 EVEX.128.66.0F.W1 2B /r
VMOVNTPD m256, ymm1 EVEX.256.66.0F.W1 2B /r
VMOVNTPD m512, zmm1 EVEX.512.66.0F.W1 2B /r
Category
sse2,cachect
Operands
Mpd,Vpd
Opcode
0x660F2B /r
CPU
P4+
Tested by
t5492 
IizVMOVNTPD:: PROC
    IiEncoding DATA=QWORD
    IiEmitOpcode 0x2B
    IiModRM /r
    IiOpEn MR
    IiDisp8EVEX FVM
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W1
    RET
.mem.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W1
    RET
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F.W1
    RET
  ENDP IizVMOVNTPD::
↑ VMOVNTDQ
Store Double Quadword Using Non-Temporal Hint
Intel reference
VMOVNTDQ m128, xmm1 VEX.128.66.0F.WIG E7 /r
VMOVNTDQ m256, ymm1 VEX.256.66.0F.WIG E7 /r
VMOVNTDQ m128, xmm1 EVEX.128.66.0F E7 /r
VMOVNTDQ m256, ymm1 EVEX.256.66.0F E7 /r
VMOVNTDQ m512, zmm1 EVEX.512.66.0F.W0 E7 /r
Category
sse2,cachect
Operands
Mdq,Vdq
Opcode
0x660FE7 /r
CPU
P4+
Tested by
t5492 
IizVMOVNTDQ:: PROC
    IiEmitOpcode 0xE7
    IiModRM /r
    IiOpEn MR
    IiDisp8EVEX FVM
    IiDispatchFormat  mem.xmm, mem.ymm, mem.zmm
.mem.xmm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F
    RET
.mem.ymm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F
    RET
.mem.zmm:
    IiEmitPrefix EVEX.512.66.0F.W0
    RET
  ENDP IizVMOVNTDQ::
↑ VMOVNTQQ
Store Double Quadword Using Non-Temporal Hint
Comment
Alias to VMOVNTDQ for better compatibility with NASM.
Intel reference
VMOVNTQQ m128, xmm1 VEX.128.66.0F.WIG E7 /r
VMOVNTQQ m256, ymm1 VEX.256.66.0F.WIG E7 /r
VMOVNTQQ m128, xmm1 EVEX.128.66.0F E7 /r
VMOVNTQQ m256, ymm1 EVEX.256.66.0F E7 /r
VMOVNTQQ m512, zmm1 EVEX.512.66.0F.W0 E7 /r
Category
sse2,cachect
Operands
Mdq,Vdq
Opcode
0x660FE7 /r
CPU
P4+
Tested by
t5492 
IizVMOVNTQQ:: PROC
    JMP IizVMOVNTDQ:
  ENDP IizVMOVNTQQ::
↑ VMOVNTDQA
Load Double Quadword Non-Temporal Aligned Hint
Intel reference
VMOVNTDQA xmm1, m128 VEX.128.66.0F38.WIG 2A /r
VMOVNTDQA ymm1, m256 VEX.256.66.0F38.WIG 2A /r
VMOVNTDQA xmm1, m128 EVEX.128.66.0F38 2A /r
VMOVNTDQA ymm1, m256 EVEX.256.66.0F38 2A /r
VMOVNTDQA zmm1, m512 EVEX.512.66.0F38.W0 2A /r
Category
sse41,cachect
Operands
Vdq,Mdq
Opcode
0x660F382A /r
CPU
C2++
Documented
D43
Tested by
t5492 
IizVMOVNTDQA:: PROC
    IiRequire SSE4.1
    IiEmitOpcode 0x2A
    IiModRM /r
    IiOpEn RM
    IiDisp8EVEX FVM
    IiModRM /r
    IiDispatchFormat  xmm.mem, ymm.mem, zmm.mem
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F38.WIG, EVEX.128.66.0F38
    RET
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F38.WIG, EVEX.256.66.0F38
    RET
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
  ENDP IizVMOVNTDQA::
↑ VMOVDDUP
Move One Double-FP and Duplicate
Intel reference
VMOVDDUP xmm1, xmm2/m64 VEX.128.F2.0F.WIG 12 /r
VMOVDDUP ymm1, ymm2/m256 VEX.256.F2.0F.WIG 12 /r
VMOVDDUP xmm1 {k1}{z}, xmm2/m64 EVEX.128.F2.0F.W1 12 /r
VMOVDDUP ymm1 {k1}{z}, ymm2/m256 EVEX.256.F2.0F.W1 12 /r
VMOVDDUP zmm1 {k1}{z}, zmm2/m512 EVEX.512.F2.0F.W1 12 /r
Category
sse3,simdfp,datamov
Operands
Vq,Wq
Opcode
0xF20F12 /r
CPU
P4++
Tested by
t5494 
IizVMOVDDUP:: PROC
    IiEncoding DATA=QWORD
    IiAllowModifier MASK
    IiDisp8EVEX DUP
    IiEmitOpcode 0x12
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.F2.0F.WIG, EVEX.128.F2.0F.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.F2.0F.WIG, EVEX.256.F2.0F.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.F2.0F.W1
    RET
  ENDP IizVMOVDDUP::
↑ VADDSUBPS
Packed Single-FP Add/Subtract
Intel reference
VADDSUBPS xmm1, xmm2, xmm3/m128 VEX.NDS.128.F2.0F.WIG D0 /r
VADDSUBPS ymm1, ymm2, ymm3/m256 VEX.NDS.256.F2.0F.WIG D0 /r
Category
sse3,simdfp,arith
Operands
Vps,Wps
Opcode
0xF20FD0 /r
CPU
P4++
Tested by
t5502 
IizVADDSUBPS:: PROC
    IiEmitOpcode 0xD0
    IiEncoding DATA=DWORD 
    IiModRM /r
    IiOpEn RVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.F2.0F.WIG
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.F2.0F.WIG
    RET
  ENDP IizVADDSUBPS::
↑ VADDSUBPD
Packed Double-FP Add/Subtract
Intel reference
VADDSUBPD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG D0 /r
VADDSUBPD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG D0 /r
Category
sse3,simdfp,arith
Operands
Vpd,Wpd
Opcode
0x660FD0 /r
CPU
P4++
Tested by
t5502 
IizVADDSUBPD:: PROC
    IiEmitOpcode 0xD0
    IiEncoding DATA=QWORD 
    IiModRM /r
    IiOpEn RVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG
    RET
  ENDP IizVADDSUBPD::
↑ VPMINUB
Minimum of Packed Unsigned Byte Integers
Intel reference
VPMINUB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F DA /r
VPMINUB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F DA /r
VPMINUB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F DA /r
VPMINUB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F DA /r
VPMINUB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F DA /r
Category
sse1,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FDA /r | 0x660FDA /r
CPU
P3+
Tested by
t5602 
IizVPMINUB:: PROC
    IiEmitOpcode 0xDA
.op:IiAllowModifier MASK
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F, EVEX.NDS.128.66.0F
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F, EVEX.NDS.256.66.0F
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F
    RET
  ENDP IizVPMINUB::
↑ VPMINUW
Minimum of Packed Unsigned Word Integers
Intel reference
VPMINUW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38 3A/r
VPMINUW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38 3A/r
VPMINUW xmm1{k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38 3A/r
VPMINUW ymm1{k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38 3A/r
VPMINUW zmm1{k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38 3A/r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F383A /r
CPU
C2++
Documented
D43
Tested by
t5602 
IizVPMINUW:: PROC
    IiEmitOpcode 0x3A
.op:IiAllowModifier MASK
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FVM 
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F38, EVEX.NDS.128.66.0F38
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F38, EVEX.NDS.256.66.0F38
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38
    RET
  ENDP IizVPMINUW::
↑ VPMINUD
Minimum of Packed Unsigned Dword Integers
Intel reference
VPMINUD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.WIG 3B /r
VPMINUD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.WIG 3B /r
VPMINUD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 3B /r
VPMINUD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 3B /r
VPMINUD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 3B /r
VPMINUD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F38.W0 3B /r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F383B /r
CPU
C2++
Documented
D43
Tested by
t5602 
IizVPMINUD:: PROC
    IiEmitOpcode 0x3B
.op:IiAllowModifier MASK,EH
    IiAllowBroadcasting DWORD
    IiOpEn RVM
    IiModRM /r 
    IiDisp8EVEX FV32
    IiDisp8MVEX Si32
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F38.WIG, EVEX.NDS.128.66.0F38.W0
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F38.WIG, EVEX.NDS.256.66.0F38.W0
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W0, MVEX.NDS.512.66.0F38.W0
    RET
  ENDP IizVPMINUD::
↑ VPMINUQ
Minimum of Packed Unsigned QWORD Integers
Intel reference
VPMINUQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 3B /r
VPMINUQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 3B /r
VPMINUQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 3B /r
Opcode
0x3B
Tested by
t5602 
IizVPMINUQ:: PROC
    IiEmitOpcode 0x3B
.op:IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiOpEn RVM
    IiModRM /r 
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W1
    RET
  ENDP IizVPMINUQ::
↑ VPMINSB
Minimum of Packed Signed Byte Integers
Intel reference
VPMINSB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38 38 /r
VPMINSB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38 38 /r
VPMINSB xmm1{k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.WIG 38 /r
VPMINSB ymm1{k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.WIG 38 /r
VPMINSB zmm1{k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.WIG 38 /r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F3838 /r
CPU
C2++
Documented
D43
Tested by
t5604 
IizVPMINSB:: PROC
    IiEmitOpcode 0x38
    JMP IizVPMINUW.op:
  ENDP IizVPMINSB::
↑ VPMINSW
Minimum of Packed Signed Word Integers
Intel reference
VPMINSW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F EA /r
VPMINSW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F EA /r
VPMINSW xmm1{k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG EA /r
VPMINSW ymm1{k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG EA /r
VPMINSW zmm1{k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG EA /r
Category
sse1,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FEA /r | 0x660FEA /r
CPU
P3+
Tested by
t5604 
IizVPMINSW:: PROC
    IiEmitOpcode 0xEA
    JMP IizVPMINUB.op:
  ENDP IizVPMINSW::
↑ VPMINSD
Minimum of Packed Signed Dword Integers
Intel reference
VPMINSD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.WIG 39 /r
VPMINSD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.WIG 39 /r
VPMINSD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 39 /r
VPMINSD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 39 /r
VPMINSD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 39 /r
VPMINSD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F38.W0 39 /r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F3839 /r
CPU
C2++
Documented
D43
Tested by
t5604 
IizVPMINSD:: PROC
    IiEmitOpcode 0x39
    JMP IizVPMINUD.op:
  ENDP IizVPMINSD::
↑ VPMINSQ
Minimum of Packed Signed QWORD Integers
Intel reference
VPMINSQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 39 /r
VPMINSQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 39 /r
VPMINSQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstEVEX.NDS.512.66.0F38.W1 39 /r
Opcode
0x39
Tested by
t5604 
IizVPMINSQ:: PROC
    IiEmitOpcode 0x39
    JMP IizVPMINUQ.op:
  ENDP IizVPMINSQ::
↑ VPMAXSB
Maximum of Packed Signed Byte Integers
Intel reference
VPMAXSB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.WIG 3C /r
VPMAXSB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.WIG 3C /r
VPMAXSB xmm1{k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.WIG 3C /r
VPMAXSB ymm1{k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.WIG 3C /r
VPMAXSB zmm1{k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.WIG 3C /r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F383C /r
CPU
C2++
Documented
D43
Tested by
t5608 
IizVPMAXSB:: PROC
    IiEmitOpcode 0x3C
    JMP IizVPMINUW.op:
  ENDP IizVPMAXSB::
↑ VPMAXSW
Maximum of Packed Signed Word Integers
Intel reference
VPMAXSW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG EE /r
VPMAXSW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG EE /r
VPMAXSW xmm1{k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG EE /r
VPMAXSW ymm1{k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG EE /r
VPMAXSW zmm1{k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG EE /r
Category
sse1,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FEE /r | 0x660FEE /r
CPU
P3+
IizVPMAXSW:: PROC
    IiEmitOpcode 0xEE
    JMP IizVPMINUB.op:
  ENDP IizVPMAXSW::
↑ VPMAXSD
Maximum of Packed Signed Dword Integers
Intel reference
VPMAXSD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.WIG 3D /r
VPMAXSD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.WIG 3D /r
VPMAXSD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 3D /r
VPMAXSD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 3D /r
VPMAXSD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 3D /r
VPMAXSD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F38.W0 3D /r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F383D /r
CPU
C2++
Documented
D43
Tested by
t5608 
IizVPMAXSD:: PROC
    IiEmitOpcode 0x3D
    JMP IizVPMINUD.op:
  ENDP IizVPMAXSD::
↑ VPMAXSQ
Maximum of Packed Signed QWORD Integers
Intel reference
VPMAXSQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 3D /r
VPMAXSQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 3D /r
VPMAXSQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 3D /r
Opcode
0x3D
Tested by
t5608 
IizVPMAXSQ:: PROC
    IiEmitOpcode 0x3D
    JMP IizVPMINUQ.op:
  ENDP IizVPMAXSQ::
↑ VPMAXUB
Maximum of Packed Unsigned Byte Integers
Intel reference
VPMAXUB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F DE /r
VPMAXUB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F DE /r
VPMAXUB xmm1{k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG DE /r
VPMAXUB ymm1{k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG DE /r
VPMAXUB zmm1{k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG DE /r
Category
sse1,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FDE /r | 0x660FDE /r
CPU
P3+
Tested by
t5606 
IizVPMAXUB:: PROC
    IiEmitOpcode 0xDE
    JMP IizVPMINUB.op:
  ENDP IizVPMAXUB::
↑ VPMAXUW
Maximum of Packed Unsigned Word Integers
Intel reference
VPMAXUW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38 3E /r
VPMAXUW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38 3E /r
VPMAXUW xmm1{k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.WIG 3E /r
VPMAXUW ymm1{k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.WIG 3E /r
VPMAXUW zmm1{k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.WIG 3E /r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F383E /r
CPU
C2++
Documented
D43
Tested by
t5606 
IizVPMAXUW:: PROC
    IiEmitOpcode 0x3E
    JMP IizVPMINUW.op:
  ENDP IizVPMAXUW::
↑ VPMAXUD
Maximum of Packed Unsigned Dword Integers
Intel reference
VPMAXUD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.WIG 3F /r
VPMAXUD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.WIG 3F /r
VPMAXUD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 3F /r
VPMAXUD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 3F /r
VPMAXUD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 3F /r
VPMAXUD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F38.W0 3F /r
Category
sse41,simdint,compar
Operands
Vdq,Wdq
Opcode
0x660F383F /r
CPU
C2++
Documented
D43
Tested by
t5606 
IizVPMAXUD:: PROC
    IiEmitOpcode 0x3F
    JMP IizVPMINUD.op:
  ENDP IizVPMAXUD::
↑ VPMAXUQ
Maximum of Packed Unsigned QWORD Integers
Intel reference
VPMAXUQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 3F /r
VPMAXUQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 3F /r
VPMAXUQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 3F /r
Opcode
0x3F
Tested by
t5606 
IizVPMAXUQ:: PROC
    IiEmitOpcode 0x3F
    JMP IizVPMINUQ.op:
  ENDP IizVPMAXUQ::
↑ VPADDB
Add Packed Integers
Intel reference
VPADDB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG FC /r
VPADDB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG FC /r
VPADDB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG FC /r
VPADDB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG FC /r
VPADDB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG FC /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FFC /r | 0x660FFC /r
CPU
PX+
Tested by
t5612 
IizVPADDB:: PROC
    IiEmitOpcode 0xFC
.op:IiEncoding DATA=BYTE
.os:IiAllowModifier MASK
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.WIG
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.WIG
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.WIG
    RET
  ENDP IizVPADDB::
↑ VPADDW
Add Packed Integers
Intel reference
VPADDW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG FD /r
VPADDW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG FD /r
VPADDW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG FD /r
VPADDW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG FD /r
VPADDW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG FD /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FFD /r | 0x660FFD /r
CPU
PX+
Tested by
t5612 
IizVPADDW:: PROC
    IiEmitOpcode 0xFD
.op:IiEncoding DATA=WORD
    JMP IizVPADDB.os:
  ENDP IizVPADDW::
↑ VPADDD
Add Packed Integers
Intel reference
VPADDD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG FE /r
VPADDD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG FE /r
VPADDD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F.W0 FE /r
VPADDD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F.W0 FE /r
VPADDD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F.W0 FE /r
VPADDD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F.W0 FE /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FFE /r | 0x660FFE /r
CPU
PX+
Tested by
t5612 
IizVPADDD:: PROC
    IiEmitOpcode 0xFE
.op:IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiDisp8EVEX FV32
    IiDisp8MVEX Si32
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W0
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W0
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.W0, MVEX.NDS.512.66.0F.W0
    RET
  ENDP IizVPADDD::
↑ VPADDQ
Add Packed Quadword Integers
Intel reference
VPADDQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG D4 /r
VPADDQ ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG D4 /r
VPADDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F.W1 D4 /r
VPADDQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F.W1 D4 /r
VPADDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F.W1 D4 /r
Category
sse2,simdint,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FD4 /r | 0x660FD4 /r
CPU
PX+
Tested by
t5612 
IizVPADDQ:: PROC
    IiEmitOpcode 0xD4
.op:IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiDisp8EVEX FV64
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.W1
    RET
  ENDP IizVPADDQ::
↑ VPADDSB
Add Packed Signed Integers with Signed Saturation
Intel reference
VPADDSB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F EC
VPADDSB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F EC
VPADDSB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG EC /r
VPADDSB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG EC /r
VPADDSB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG EC /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FEC /r | 0x660FEC /r
CPU
PX+
Tested by
t5616 
IizVPADDSB:: PROC
    IiEmitOpcode 0xEC
    JMP IizVPADDB.op:
    RET
  ENDP IizVPADDSB::
↑ VPADDSW
Add Packed Signed Integers with Signed Saturation
Intel reference
VPADDSW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F ED
VPADDSW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F ED
VPADDSW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG ED /r
VPADDSW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG ED /r
VPADDSW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG ED /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FED /r | 0x660FED /r
CPU
PX+
Tested by
t5616 
IizVPADDSW:: PROC
    IiEmitOpcode 0xED
    JMP IizVPADDW.op:
  ENDP IizVPADDSW::
↑ VPSUBB
Subtract Packed Integers
Intel reference
VPSUBB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG F8 /r
VPSUBB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG F8 /r
VPSUBB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG F8 /r
VPSUBB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG F8 /r
VPSUBB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG F8 /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FF8 /r | 0x660FF8 /r
CPU
PX+
Tested by
t5614 
IizVPSUBB:: PROC
    IiEmitOpcode 0xF8
    JMP IizVPADDB.op:
  ENDP IizVPSUBB::
↑ VPSUBW
Subtract Packed Integers
Intel reference
VPSUBW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG F9 /r
VPSUBW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG F9 /r
VPSUBW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG F9 /r
VPSUBW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG F9 /r
VPSUBW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG F9 /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FF9 /r | 0x660FF9 /r
CPU
PX+
Tested by
t5614 
IizVPSUBW:: PROC
    IiEmitOpcode 0xF9
    JMP IizVPADDW.op:
  ENDP IizVPSUBW::
↑ VPSUBD
Subtract Packed Integers
Intel reference
VPSUBD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG FA /r
VPSUBD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG FA /r
VPSUBD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F.W0 FA /r
VPSUBD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F.W0 FA /r
VPSUBD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F.W0 FA /r
VPSUBD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F.W0 FA /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FFA /r | 0x660FFA /r
CPU
PX+
Tested by
t5614 
IizVPSUBD:: PROC
    IiEmitOpcode 0xFA
    JMP IizVPADDD.op:
  ENDP IizVPSUBD::
↑ VPSUBQ
Subtract Packed Quadword Integers
Intel reference
VPSUBQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG FB /r
VPSUBQ ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG FB /r
VPSUBQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F.W1 FB /r
VPSUBQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F.W1 FB /r
VPSUBQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F.W1 FB/r
Category
sse2,simdint,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FFB /r | 0x660FFB /r
CPU
P4+
Tested by
t5614 
IizVPSUBQ:: PROC
    IiEmitOpcode 0xFB
    JMP IizVPADDQ.op:
  ENDP IizVPSUBQ::
↑ VPSUBSB
Subtract Packed Signed Integers with Signed Saturation
Intel reference
VPSUBSB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F E8 /r
VPSUBSB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F E8 /r
VPSUBSB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG E8 /r
VPSUBSB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG E8 /r
VPSUBSB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG E8 /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FE8 /r | 0x660FE8 /r
CPU
PX+
Tested by
t5616 
IizVPSUBSB:: PROC
    IiEmitOpcode 0xE8
    JMP IizVPADDB.op:
  ENDP IizVPSUBSB::
↑ VPSUBSW
Subtract Packed Signed Integers with Signed Saturation
Intel reference
VPSUBSW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F E9 /r
VPSUBSW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F E9 /r
VPSUBSW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG E9 /r
VPSUBSW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG E9 /r
VPSUBSW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG E9 /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FE9 /r | 0x660FE9 /r
CPU
PX+
Tested by
t5616 
IizVPSUBSW:: PROC
    IiEmitOpcode 0xE9
    JMP IizVPADDW.op:
  ENDP IizVPSUBSW::
↑ VPADDUSB
Add Packed Unsigned Integers with Unsigned Saturation
Intel reference
VPADDUSB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F DC
VPADDUSB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F DC
VPADDUSB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG DC /r
VPADDUSB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG DC /r
VPADDUSB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG DC /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FDC /r | 0x660FDC /r
CPU
PX+
Tested by
t5618 
IizVPADDUSB:: PROC
    IiEmitOpcode 0xDC
    JMP IizVPADDB.op:
  ENDP IizVPADDUSB::
↑ VPADDUSW
Add Packed Unsigned Integers with Unsigned Saturation
Intel reference
VPADDUSW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F DD
VPADDUSW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F DD
VPADDUSW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG DD /r
VPADDUSW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG DD /r
VPADDUSW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG DD /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FDD /r | 0x660FDD /r
CPU
PX+
Tested by
t5618 
IizVPADDUSW:: PROC
    IiEmitOpcode 0xDD
    JMP IizVPADDW.op:
  ENDP IizVPADDUSW::
↑ VPSUBUSB
Subtract Packed Unsigned Integers with Unsigned Saturation
Intel reference
VPSUBUSB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F D8 /r
VPSUBUSB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F D8 /r
VPSUBUSB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG D8 /r
VPSUBUSB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG D8 /r
VPSUBUSB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG D8 /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FD8 /r | 0x660FD8 /r
CPU
PX+
Tested by
t5618 
IizVPSUBUSB:: PROC
    IiEmitOpcode 0xD8
    JMP IizVPADDB.op:
  ENDP IizVPSUBUSB::
↑ VPSUBUSW
Subtract Packed Signed Integers with Signed Saturation
Intel reference
VPSUBUSW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F D9 /r
VPSUBUSW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F D9 /r
VPSUBUSW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG D9 /r
VPSUBUSW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG D9 /r
VPSUBUSW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG D9 /r
Category
mmx,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FE9 /r | 0x660FE9 /r
CPU
PX+
Tested by
t5618 
IizVPSUBUSW:: PROC
    IiEmitOpcode 0xD9
    JMP IizVPADDW.op:
  ENDP IizVPSUBUSW::
↑ VHADDPS
Packed Single-FP Horizontal Add
Intel reference
VHADDPS xmm1, xmm2, xmm3/m128 VEX.NDS.128.F2.0F.WIG 7C /r
VHADDPS ymm1, ymm2, ymm3/m256 VEX.NDS.256.F2.0F.WIG 7C /r
Category
sse3,simdfp,arith
Operands
Vps,Wps
Opcode
0xF20F7C /r
CPU
P4++
Tested by
t5610 
IizVHADDPS:: PROC
    IiEmitOpcode 0x7C
.op:IiEncoding DATA=DWORD
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.F2.0F.WIG
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.F2.0F.WIG
    RET
  ENDP IizVHADDPS::
↑ VHADDPD
Packed Double-FP Horizontal Add
Intel reference
VHADDPD xmm1,xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG 7C /r
VHADDPD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG 7C /r
Category
sse3,simdfp,arith
Operands
Vpd,Wpd
Opcode
0x660F7C /r
CPU
P4++
Tested by
t5610 
IizVHADDPD:: PROC
    IiEmitOpcode 0x7C
.op:IiEncoding DATA=QWORD
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG
    RET
  ENDP IizVHADDPD::
↑ VHSUBPS
Packed Single-FP Horizontal Subtract
Intel reference
VHSUBPS xmm1, xmm2, xmm3/m128 VEX.NDS.128.F2.0F.WIG 7D /r
VHSUBPS ymm1, ymm2, ymm3/m256 VEX.NDS.256.F2.0F.WIG 7D /r
Category
sse3,simdfp,arith
Operands
Vps,Wps
Opcode
0xF20F7D /r
CPU
P4++
Tested by
t5610 
IizVHSUBPS:: PROC
    IiEmitOpcode 0x7D
    JMP IizVHADDPS.op:
  ENDP IizVHSUBPS::
↑ VHSUBPD
Packed Double-FP Horizontal Subtract
Intel reference
VHSUBPD xmm1,xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG 7D /r
VHSUBPD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG 7D /r
Category
sse3,simdfp,arith
Operands
Vpd,Wpd
Opcode
0x660F7D /r
CPU
P4++
Tested by
t5610 
IizVHSUBPD:: PROC
    IiEmitOpcode 0x7D
    JMP IizVHADDPD.op:
  ENDP IizVHSUBPD::
↑ VPSRLW
Shift Packed Data Right Logical
Intel reference
VPSRLW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG D1 /r
VPSRLW xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 71 /2 ib
VPSRLW ymm1, ymm2, xmm3/m128 VEX.NDS.256.66.0F.WIG D1 /r
VPSRLW ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 71 /2 ib
VPSRLW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG D1 /r
VPSRLW ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.WIG D1 /r
VPSRLW zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.WIG D1 /r
VPSRLW xmm1 {k1}{z}, xmm2/m128, imm8 EVEX.NDD.128.66.0F.WIG 71 /2 ib
VPSRLW ymm1 {k1}{z}, ymm2/m256, imm8 EVEX.NDD.256.66.0F.WIG 71 /2 ib
VPSRLW zmm1 {k1}{z}, zmm2/m512, imm8 EVEX.NDD.512.66.0F.WIG 71 /2 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F71 /2 | 0x660F71 /2 | 0x0FD1 /r | 0x660FD1 /r
CPU
PX+
Tested by
t5622 
IizVPSRLW:: PROC
    MOV AL,0xD1
    MOV BL,0x71
    MOV ECX,iiPpgModRMd | 2<<28
.op:IiAllowModifier MASK
    IiEncoding DATA=WORD
    CMP DL,imm
    JE .I:
    IiOpEn RVM
    IiEmitOpcode EAX
    IiModRM /r
    IiDisp8EVEX M128
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.xmm, ymm.ymm.mem, zmm.zmm.xmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.WIG
    RET
.ymm.ymm.xmm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.WIG
    RET
.zmm.zmm.xmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.WIG
    RET
.I: IiOpEn VM
    IiEmitOpcode EBX
    IiModRM ECX
    IiEmitImm Operand3, BYTE
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.imm, ymm.ymm.imm, xmm.mem.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
    IiEmitPrefix VEX.NDD.128.66.0F.WIG, EVEX.NDD.128.66.0F.WIG
    RET
.xmm.mem.imm:
    IiEmitPrefix EVEX.NDD.128.66.0F.WIG
    RET
.ymm.ymm.imm:
    IiEmitPrefix VEX.NDD.256.66.0F.WIG, EVEX.NDD.256.66.0F.WIG
    RET
.ymm.mem.imm:
    IiEmitPrefix EVEX.NDD.256.66.0F.WIG
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.NDD.512.66.0F.WIG
    RET
  ENDP IizVPSRLW::
↑ VPSRLD
Shift Double Quadword Right Logical
Intel reference
VPSRLD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG D2 /r
VPSRLD xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 72 /2 ib
VPSRLD ymm1, ymm2, xmm3/m128 VEX.NDS.256.66.0F.WIG D2 /r
VPSRLD ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 72 /2 ib
VPSRLD xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.W0 D2 /r
VPSRLD ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.W0 D2 /r
VPSRLD zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.W0 D2 /r
VPSRLD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8 EVEX.NDD.128.66.0F.W0 72 /2 ib
VPSRLD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8 EVEX.NDD.256.66.0F.W0 72 /2 ib
VPSRLD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8 EVEX.NDD.512.66.0F.W0 72 /2 ib
VPSRLD zmm1 {k1}, zmm2/m512/m32bcst, imm8 MVEX.NDD.512.66.0F.W0 72 /2 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F72 /2 | 0x660F72 /2 | 0x0FD2 /r | 0x660FD2 /r
CPU
PX+
Tested by
t5622 
IizVPSRLD:: PROC
    MOV AL,0xD2
    MOV BL,0x72
    MOV ECX,iiPpgModRMd | 2<<28
.op:IiAllowModifier MASK
    IiEncoding DATA=DWORD
    CMP DL,imm
    JE .I:
    IiOpEn RVM
    IiEmitOpcode EAX
    IiModRM /r
    IiDisp8EVEX M128
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.xmm, ymm.ymm.mem, zmm.zmm.xmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W0
    RET
.ymm.ymm.xmm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W0
    RET
.zmm.zmm.xmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.W0
    RET
.I: IiOpEn VM
    IiEmitOpcode EBX
    IiModRM ECX
    IiEmitImm Operand3, BYTE
    IiAllowBroadcasting DWORD, Operand=DH
    IiDisp8EVEX FV32
    IiDisp8MVEX Si32
    IiDispatchFormat  xmm.xmm.imm, ymm.ymm.imm, xmm.mem.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.mem.imm:
    IiEmitPrefix EVEX.NDD.128.66.0F.W0
    RET
.xmm.xmm.imm:
    IiEmitPrefix VEX.NDD.128.66.0F.WIG, EVEX.NDD.128.66.0F.W0
    RET
.ymm.mem.imm:
    IiEmitPrefix EVEX.NDD.256.66.0F.W0
    RET
.ymm.ymm.imm:
    IiEmitPrefix VEX.NDD.256.66.0F.WIG, EVEX.NDD.256.66.0F.W0
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.NDD.512.66.0F.W0, MVEX.NDD.512.66.0F.W0
    RET
  ENDP IizVPSRLD::
↑ VPSRLQ
Shift Packed Data Right Logical
Intel reference
VPSRLQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG D3 /r
VPSRLQ xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 73 /2 ib
VPSRLQ ymm1, ymm2, xmm3/m128 VEX.NDS.256.66.0F.WIG D3 /r
VPSRLQ ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 73 /2 ib
VPSRLQ xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.W1 D3 /r
VPSRLQ ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.W1 D3 /r
VPSRLQ zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.W1 D3 /r
VPSRLQ xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8 EVEX.NDD.128.66.0F.W1 73 /2 ib
VPSRLQ ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8 EVEX.NDD.256.66.0F.W1 73 /2 ib
VPSRLQ zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8 EVEX.NDD.512.66.0F.W1 73 /2 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F73 /2 | 0x660F73 /2 | 0x0FD3 /r | 0x660FD3 /r
CPU
PX+
Tested by
t5622 
IizVPSRLQ:: PROC
    MOV AL,0xD3
    MOV BL,0x73
    MOV ECX,iiPpgModRMd | 2<<28
.op:IiAllowModifier MASK
    IiEncoding DATA=QWORD
    CMP DL,imm
    JE .I:
    IiOpEn RVM
    IiEmitOpcode EAX
    IiModRM /r
    IiDisp8EVEX M128
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.xmm, ymm.ymm.mem, zmm.zmm.xmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W1
    RET
.ymm.ymm.xmm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W1
    RET
.zmm.zmm.xmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.W1
    RET
.I: IiOpEn VM
    IiEmitOpcode EBX
    IiModRM ECX
    IiEmitImm Operand3, BYTE
    IiAllowBroadcasting QWORD, Operand=DH
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm.imm, ymm.ymm.imm, xmm.mem.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.mem.imm:
    IiEmitPrefix EVEX.NDD.128.66.0F.W1
    RET
.xmm.xmm.imm:
    IiEmitPrefix VEX.NDD.128.66.0F.WIG, EVEX.NDD.128.66.0F.W1
    RET
.ymm.mem.imm:
    IiEmitPrefix EVEX.NDD.256.66.0F.W1
    RET
.ymm.ymm.imm:
    IiEmitPrefix VEX.NDD.256.66.0F.WIG, EVEX.NDD.256.66.0F.W1
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.NDD.512.66.0F.W1
    RET
  ENDP IizVPSRLQ::
↑ VPSRLDQ
Shift Double Quadword Right Logical
Intel reference
VPSRLDQ xmm1, xmm2, imm8 VEX.NDD.128.66.0F 73 /3 ib
VPSRLDQ ymm1, ymm2, imm8 VEX.NDD.256.66.0F 73 /3 ib
VPSRLDQ xmm1, xmm2/m128, imm8 EVEX.NDD.128.66.0F.WIG 73 /3 ib
VPSRLDQ ymm1, ymm2/m256, imm8 EVEX.NDD.256.66.0F.WIG 73 /3 ib
VPSRLDQ zmm1, zmm2/m512, imm8 EVEX.NDD.512.66.0F.WIG 73 /3 ib
Category
sse2,simdint,shift
Operands
Udq,Ib
Opcode
0x660F73 /3
CPU
P4+
Tested by
t5622 
IizVPSRLDQ:: PROC
    MOV ECX,iiPpgModRMd | 3<<28
    MOV BL,0x73
.d: IiEmitOpcode EBX
    IiModRM ECX
    IiOpEn VM
    IiEmitImm Operand3, BYTE
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.imm, ymm.ymm.imm, xmm.mem.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.mem.imm:
    IiEmitPrefix EVEX.NDD.128.66.0F.WIG
    RET
.xmm.xmm.imm:
    IiEmitPrefix VEX.NDD.128.66.0F, EVEX.NDD.128.66.0F.WIG
    RET
.ymm.mem.imm:
    IiEmitPrefix EVEX.NDD.256.66.0F.WIG
    RET
.ymm.ymm.imm:
    IiEmitPrefix VEX.NDD.256.66.0F, EVEX.NDD.256.66.0F.WIG
    RET
.zmm.mem.imm:
    IiEmitPrefix EVEX.NDD.512.66.0F.WIG
    RET
.zmm.zmm.imm:
    IiEmitPrefix EVEX.NDD.512.66.0F.WIG
    RET
  ENDP IizVPSRLDQ::
↑ VPSRAW
Shift Packed Data Right Arithmetic
Intel reference
VPSRAW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG E1 /r
VPSRAW xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 71 /4 ib
VPSRAW ymm1, ymm2, ymm3/m128 VEX.NDS.256.66.0F.WIG E1 /r
VPSRAW ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 71 /4 ib
VPSRAW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG E1 /r
VPSRAW ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.WIG E1 /r
VPSRAW zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.WIG E1 /r
VPSRAW xmm1 {k1}{z}, xmm2/m128, imm8 EVEX.NDD.128.66.0F.WIG 71 /4 ib
VPSRAW ymm1 {k1}{z}, ymm2/m256, imm8 EVEX.NDD.256.66.0F.WIG 71 /4 ib
VPSRAW zmm1 {k1}{z}, zmm2/m512, imm8 EVEX.NDD.512.66.0F.WIG 71 /4 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F71 /4 | 0x660F71 /4 | 0x0FE1 /r | 0x660FE1 /r
CPU
PX+
Tested by
t5626 
IizVPSRAW:: PROC
    MOV AL,0xE1
    MOV BL,0x71
    MOV ECX,iiPpgModRMd | 4<<28
    JMP IizVPSRLW.op:
  ENDP IizVPSRAW::
↑ VPSRAD
Shift Packed Data Right Arithmetic
Intel reference
VPSRAD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG E2 /r
VPSRAD xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 72 /4 ib
VPSRAD ymm1, ymm2, xmm3/m128 VEX.NDS.256.66.0F.WIG E2 /r
VPSRAD ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 72 /4 ib
VPSRAD xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.W0 E2 /r
VPSRAD ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.W0 E2 /r
VPSRAD zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.W0 E2 /r
VPSRAD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8 EVEX.NDD.128.66.0F.W0 72 /4 ib
VPSRAD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8 EVEX.NDD.256.66.0F.W0 72 /4 ib
VPSRAD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8 EVEX.NDD.512.66.0F.W0 72 /4 ib
VPSRAD zmm1 {k1}, zmm2/m512/m32bcst, imm8 MVEX.NDD.512.66.0F.W0 72 /4 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F72 /4 | 0x660F72 /4 | 0x0FE2 /r | 0x660FE2 /r
CPU
PX+
Tested by
t5626 
IizVPSRAD:: PROC
    MOV AL,0xE2
    MOV BL,0x72
    MOV ECX,iiPpgModRMd | 4<<28
    JMP IizVPSRLD.op:
  ENDP IizVPSRAD::
↑ VPSRAQ
Bit Shift Arithmetic Right
Intel reference
VPSRAQ xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.W1 E2 /r
VPSRAQ ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.W1 E2 /r
VPSRAQ zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.W1 E2 /r
VPSRAQ xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8 EVEX.NDD.128.66.0F.W1 72 /4 ib
VPSRAQ ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8 EVEX.NDD.256.66.0F.W1 72 /4 ib
VPSRAQ zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8 EVEX.NDD.512.66.0F.W1 72 /4 ib
Opcode
0xE2 | 0x72
Tested by
t5626 
IizVPSRAQ:: PROC
    IiAllowModifier MASK
    IiEncoding DATA=QWORD
    CMP DL,imm
    JE .I:
    IiOpEn RVM
    IiEmitOpcode 0xE2
    IiModRM /r
    IiDisp8EVEX M128
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.xmm, ymm.ymm.mem, zmm.zmm.xmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F.W1
    RET
.ymm.ymm.xmm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F.W1
    RET
.zmm.zmm.xmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.W1
    RET
.I: IiOpEn VM
    IiEmitOpcode 0x72
    IiModRM /4
    IiEmitImm Operand3, BYTE
    IiAllowBroadcasting QWORD, Operand=DH
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
    IiEmitPrefix EVEX.NDD.128.66.0F.W1
    RET
.ymm.ymm.imm:
.ymm.mem.imm:
    IiEmitPrefix EVEX.NDD.256.66.0F.W1
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.NDD.512.66.0F.W1
    RET
  ENDP IizVPSRAQ::
↑ VPSLLW
Shift Packed Data Left Logical
Intel reference
VPSLLW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG F1 /r
VPSLLW xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 71 /6 ib
VPSLLW ymm1, ymm2, xmm3/m128 VEX.NDS.256.66.0F.WIG F1 /r
VPSLLW ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 71 /6 ib
VPSLLW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG F1 /r
VPSLLW ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.WIG F1 /r
VPSLLW zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.WIG F1 /r
VPSLLW xmm1 {k1}{z}, xmm2/m128, imm8 EVEX.NDD.128.66.0F.WIG 71 /6 ib
VPSLLW ymm1 {k1}{z}, ymm2/m256, imm8 EVEX.NDD.256.66.0F.WIG 71 /6 ib
VPSLLW zmm1 {k1}{z}, zmm2/m512, imm8 EVEX.NDD.512.66.0F.WIG 71 /6 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F71 /6 | 0x660F71 /6 | 0x0FF1 /r | 0x660FF1 /r
CPU
PX+
Tested by
t5624 
IizVPSLLW:: PROC
    MOV AL,0xF1
    MOV BL,0x71
    MOV ECX,iiPpgModRMd | 6<<28
    JMP IizVPSRLW.op:
  ENDP IizVPSLLW::
↑ VPSLLD
Shift Packed Data Left Logical
Intel reference
VPSLLD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG F2 /r
VPSLLD xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 72 /6 ib
VPSLLD ymm1, ymm2, xmm3/m128 VEX.NDS.256.66.0F.WIG F2 /r
VPSLLD ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 72 /6 ib
VPSLLD xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.W0 F2 /r
VPSLLD ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.W0 F2 /r
VPSLLD zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.W0 F2 /r
VPSLLD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8 EVEX.NDD.128.66.0F.W0 72 /6 ib
VPSLLD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8 EVEX.NDD.256.66.0F.W0 72 /6 ib
VPSLLD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8 EVEX.NDD.512.66.0F.W0 72 /6 ib
VPSLLD zmm1 {k1}, zmm2/m512/m32bcst, imm8 MVEX.NDD.512.66.0F.W0 72 /6 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F72 /6 | 0x660F72 /6 | 0x0FF2 /r | 0x660FF2 /r
CPU
PX+
Tested by
t5624 
IizVPSLLD:: PROC
    MOV AL,0xF2
    MOV BL,0x72
    MOV ECX,iiPpgModRMd | 6<<28
    JMP IizVPSRLD.op:
  ENDP IizVPSLLD::
↑ VPSLLQ
Shift Packed Data Left Logical
Intel reference
VPSLLQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG F3 /r
VPSLLQ xmm1, xmm2, imm8 VEX.NDD.128.66.0F.WIG 73 /6 ib
VPSLLQ ymm1, ymm2, xmm3/m128 VEX.NDS.256.66.0F.WIG F3 /r
VPSLLQ ymm1, ymm2, imm8 VEX.NDD.256.66.0F.WIG 73 /6 ib
VPSLLQ xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.W1 F3 /r
VPSLLQ ymm1 {k1}{z}, ymm2, xmm3/m128 EVEX.NDS.256.66.0F.W1 F3 /r
VPSLLQ zmm1 {k1}{z}, zmm2, xmm3/m128 EVEX.NDS.512.66.0F.W1 F3 /r
VPSLLQ xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8 EVEX.NDD.128.66.0F.W1 73 /6 ib
VPSLLQ ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8 EVEX.NDD.256.66.0F.W1 73 /6 ib
VPSLLQ zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8 EVEX.NDD.512.66.0F.W1 73 /6 ib
Category
mmx,shift
Operands
Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
0x0F73 /6 | 0x660F73 /6 | 0x0FF3 /r | 0x660FF3 /r
CPU
PX+
Tested by
t5624 
IizVPSLLQ:: PROC
    MOV AL,0xF3
    MOV BL,0x73
    MOV ECX,iiPpgModRMd | 6<<28
    JMP IizVPSRLQ.op:
  ENDP IizVPSLLQ::
↑ VPSLLDQ
Shift Double Quadword Left Logical
Intel reference
VPSLLDQ xmm1, xmm2, imm8 VEX.NDD.128.66.0F 73 /7 ib
VPSLLDQ ymm1, ymm2, imm8 VEX.NDD.256.66.0F 73 /7 ib
VPSLLDQ xmm1,xmm2/ m128, imm8 EVEX.NDD.128.66.0F 73 /7 ib
VPSLLDQ ymm1, ymm2/m256, imm8 EVEX.NDD.256.66.0F 73 /7 ib
VPSLLDQ zmm1, zmm2/m512, imm8 EVEX.NDD.512.66.0F 73 /7 ib
Category
sse2,simdint,shift
Operands
Udq,Ib
Opcode
0x660F73 /7
CPU
P4+
Tested by
t5624 
IizVPSLLDQ:: PROC
    MOV ECX,iiPpgModRMd | 7<<28
    MOV BL,0x73
    JMP IizVPSRLDQ.d:
  ENDP IizVPSLLDQ::
↑ VPSRLVW
Variable Bit Shift Right Logical WORD
Intel reference
VPSRLVW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.W1 10 /r
VPSRLVW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.W1 10 /r
VPSRLVW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.W1 10 /r
Opcode
0x10
Tested by
t5632 
IizVPSRLVW:: PROC
    IiEmitOpcode 0x10
.op:IiEncoding DATA=WORD
    IiAllowModifier MASK
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W1
    RET
  ENDP IizVPSRLVW::
↑ VPSRLVD
Variable Bit Shift Right Logical DWORD
Description
VPSRLVD
Intel reference
VPSRLVD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.W0 45 /r
VPSRLVD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.W0 45 /r
VPSRLVD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 45 /r
VPSRLVD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 45 /r
VPSRLVD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 45 /r
VPSRLVD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F38.W0 45 /r
Opcode
0x45
Tested by
t5632 
IizVPSRLVD:: PROC
    IiEmitOpcode 0x45
.op:IiEncoding DATA=DWORD
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV32
    IiDisp8MVEX Si32
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F38.W0, EVEX.NDS.128.66.0F38.W0
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F38.W0, EVEX.NDS.256.66.0F38.W0
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W0, MVEX.NDS.512.66.0F38.W0
    RET
  ENDP IizVPSRLVD::
↑ VPSRLVQ
Variable Bit Shift Right Logical QWORD
Description
VPSRLVQ
Intel reference
VPSRLVQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.W1 45 /r
VPSRLVQ ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.W1 45 /r
VPSRLVQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 45 /r
VPSRLVQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 45 /r
VPSRLVQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 45 /r
Opcode
0x45
Tested by
t5632 
IizVPSRLVQ:: PROC
    IiEmitOpcode 0x45
.op:IiEncoding DATA=QWORD
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F38.W1, EVEX.NDS.128.66.0F38.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F38.W1, EVEX.NDS.256.66.0F38.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W1
    RET
  ENDP IizVPSRLVQ::
↑ VPSRAVW
Variable Bit Shift Right Arithmetic WORD
Intel reference
VPSRAVW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.W1 11 /r
VPSRAVW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.W1 11 /r
VPSRAVW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.W1 11 /r
Opcode
0x11
Tested by
t5634 
IizVPSRAVW:: PROC
    IiEmitOpcode 0x11
    JMP IizVPSRLVW.op:
    RET
  ENDP IizVPSRAVW::
↑ VPSRAVD
Variable Bit Shift Right Arithmetic DWORD
Description
VPSRAVD
Intel reference
VPSRAVD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.W0 46 /r
VPSRAVD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.W0 46 /r
VPSRAVD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 46 /r
VPSRAVD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 46 /r
VPSRAVD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 46 /r
VPSRAVD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F38.W0 46 /r
Opcode
0x46
Tested by
t5634 
IizVPSRAVD:: PROC
    IiEmitOpcode 0x46
    JMP IizVPSRLVD.op:
  ENDP IizVPSRAVD::
↑ VPSRAVQ
Variable Bit Shift Right Arithmetic QWORD
Intel reference
VPSRAVQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 46 /r
VPSRAVQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 46 /r
VPSRAVQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 46 /r
Opcode
0x46
Tested by
t5634 
IizVPSRAVQ:: PROC
    IiEmitOpcode 0x46
    IiEncoding DATA=QWORD
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix EVEX.NDS.128.66.0F38.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix EVEX.NDS.256.66.0F38.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.W1
    RET
  ENDP IizVPSRAVQ::
↑ VPSLLVW
Variable Bit Shift Left Logical WORD
Intel reference
VPSLLVW xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.W1 12 /r
VPSLLVW ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.W1 12 /r
VPSLLVW zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.W1 12 /r
Opcode
0x12
Tested by
t5636 
IizVPSLLVW:: PROC
    IiEmitOpcode 0x12
    JMP IizVPSRLVW.op:
  ENDP IizVPSLLVW::
↑ VPSLLVD
Variable Bit Shift Left Logical DWORD
Description
VPSLLVD
Intel reference
VPSLLVD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.W0 47 /r
VPSLLVD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.W0 47 /r
VPSLLVD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst EVEX.NDS.128.66.0F38.W0 47 /r
VPSLLVD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst EVEX.NDS.256.66.0F38.W0 47 /r
VPSLLVD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst EVEX.NDS.512.66.0F38.W0 47 /r
VPSLLVD zmm1 {k1}, zmm2, zmm3/m512/m32bcst MVEX.NDS.512.66.0F38.W0 47 /r
Opcode
0x47
Tested by
t5636 
IizVPSLLVD:: PROC
    IiEmitOpcode 0x47
    JMP IizVPSRLVD.op:
  ENDP IizVPSLLVD::
↑ VPSLLVQ
Variable Bit Shift Left Logical QWORD
Description
VPSLLVQ
Intel reference
VPSLLVQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.W1 47 /r
VPSLLVQ ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.W1 47 /r
VPSLLVQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F38.W1 47 /r
VPSLLVQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F38.W1 47 /r
VPSLLVQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F38.W1 47 /r
Opcode
0x47
Tested by
t5636 
IizVPSLLVQ:: PROC
    IiEmitOpcode 0x47
    JMP IizVPSRLVQ.op:
  ENDP IizVPSLLVQ::
↑ VPABSB
Packed Absolute Value
Intel reference
VPABSB xmm1, xmm2/m128 VEX.128.66.0F38.WIG 1C /r
VPABSB ymm1, ymm2/m256 VEX.256.66.0F38.WIG 1C /r
VPABSB xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F38 1C /r
VPABSB ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F38 1C /r
VPABSB zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F38 1C /r
Category
ssse3,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0F381C /r | 0x660F381C /r
CPU
C2+
Tested by
t5640 
IizVPABSB:: PROC
    IiEncoding DATA=BYTE
    IiAllowModifier MASK
    IiEmitOpcode 0x1C
    IiOpEn RM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F38.WIG, EVEX.128.66.0F38
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F38.WIG, EVEX.256.66.0F38
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38
    RET
  ENDP IizVPABSB::
↑ VPABSW
Packed Absolute Value
Intel reference
VPABSW xmm1, xmm2/m128 VEX.128.66.0F38.WIG 1D /r
VPABSW ymm1, ymm2/m256 VEX.256.66.0F38.WIG 1D /r
VPABSW xmm1 {k1}{z}, xmm2/m128 EVEX.128.66.0F38 1D /r
VPABSW ymm1 {k1}{z}, ymm2/m256 EVEX.256.66.0F38 1D /r
VPABSW zmm1 {k1}{z}, zmm2/m512 EVEX.512.66.0F38 1D /r
Category
ssse3,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0F381D /r | 0x660F381D /r
CPU
C2+
Tested by
t5640 
IizVPABSW:: PROC
    IiEncoding DATA=WORD
    IiAllowModifier MASK
    IiEmitOpcode 0x1D
    IiOpEn RM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F38.WIG, EVEX.128.66.0F38
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F38.WIG, EVEX.256.66.0F38
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38
    RET
  ENDP IizVPABSW::
↑ VPABSD
Packed Absolute Value
Intel reference
VPABSD xmm1, xmm2/m128 VEX.128.66.0F38.WIG 1E /r
VPABSD ymm1, ymm2/m256 VEX.256.66.0F38.WIG 1E /r
VPABSD xmm1 {k1}{z}, xmm2/m128/m32bcst EVEX.128.66.0F38.W0 1E /r
VPABSD ymm1 {k1}{z}, ymm2/m256/m32bcst EVEX.256.66.0F38.W0 1E /r
VPABSD zmm1 {k1}{z}, zmm2/m512/m32bcst EVEX.512.66.0F38.W0 1E /r
Category
ssse3,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0F381E /r | 0x660F381E /r
CPU
C2+
Tested by
t5640 
IizVPABSD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD
    IiEmitOpcode 0x1E
    IiOpEn RM
    IiModRM /r
    IiDisp8EVEX FV32
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix VEX.128.66.0F38.WIG, EVEX.128.66.0F38.W0
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix VEX.256.66.0F38.WIG, EVEX.256.66.0F38.W0
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W0
    RET
  ENDP IizVPABSD::
↑ VPABSQ
Packed Absolute Value
Intel reference
VPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcst EVEX.128.66.0F38.W1 1F /r
VPABSQ ymm1 {k1}{z}, ymm2/m256/m64bcst EVEX.256.66.0F38.W1 1F /r
VPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst EVEX.512.66.0F38.W1 1F /r
Opcode
0x1F
Tested by
t5640 
IizVPABSQ:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiEmitOpcode 0x1F
    IiOpEn RM
    IiModRM /r
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
    IiEmitPrefix EVEX.128.66.0F38.W1
    RET
.ymm.ymm:
.ymm.mem:
    IiEmitPrefix EVEX.256.66.0F38.W1
    RET
.zmm.zmm:
.zmm.mem:
    IiEmitPrefix EVEX.512.66.0F38.W1
    RET
  ENDP IizVPABSQ::
↑ VPMULUDQ
Multiply Packed Unsigned DW Integers
Intel reference
VPMULUDQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG F4 /r
VPMULUDQ ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG F4 /r
VPMULUDQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst EVEX.NDS.128.66.0F.W1 F4 /r
VPMULUDQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst EVEX.NDS.256.66.0F.W1 F4 /r
VPMULUDQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst EVEX.NDS.512.66.0F.W1 F4 /r
Category
sse2,simdint,arith
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FF4 /r | 0x660FF4 /r
CPU
P4+
Tested by
t5642 t5680 
IizVPMULUDQ:: PROC
    IiEmitOpcode 0xF4
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W1
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W1
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.W1
    RET
  ENDP IizVPMULUDQ::
↑ VPMADDWD
Multiply and Add Packed Integers
Intel reference
VPMADDWD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F F5 /r
VPMADDWD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F F5 /r
VPMADDWD xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG F5 /r
VPMADDWD ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG F5 /r
VPMADDWD zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F.WIG F5 /r
Category
mmx,arith
Operands
Pq,Qd | Vdq,Wdq
Opcode
0x0FF5 /r | 0x660FF5 /r
CPU
PX+
Tested by
t5642 
IizVPMADDWD:: PROC
    IiEmitOpcode 0xF5
    IiAllowModifier MASK
.op:IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F, EVEX.NDS.128.66.0F.WIG
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F, EVEX.NDS.256.66.0F.WIG
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F.WIG
    RET
  ENDP IizVPMADDWD::
↑ VPSADBW
Compute Sum of Absolute Differences
Intel reference
VPSADBW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F F6 /r
VPSADBW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F F6 /r
VPSADBW xmm1, xmm2, xmm3/m128 EVEX.NDS.128.66.0F.WIG F6 /r
VPSADBW ymm1, ymm2, ymm3/m256 EVEX.NDS.256.66.0F.WIG F6 /r
VPSADBW zmm1, zmm2, zmm3/m512EVEX.NDS.512.66.0F.WIG F6 /r
Category
sse1,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0FF6 /r | 0x660FF6 /r
CPU
P3+
Tested by
t5642 
IizVPSADBW:: PROC
    IiEmitOpcode 0xF6
    JMP IizVPMADDWD.op:
  ENDP IizVPSADBW::
↑ VSHUFPS
Shuffle Packed Single-FP Values
Intel reference
VSHUFPS xmm1, xmm2, xmm3/m128, imm8 VEX.NDS.128.0F.WIG C6 /r ib
VSHUFPS ymm1, ymm2, ymm3/m256, imm8 VEX.NDS.256.0F.WIG C6 /r ib
VSHUFPS xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst, imm8 EVEX.NDS.128.0F.W0 C6 /r ib
VSHUFPS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8 EVEX.NDS.256.0F.W0 C6 /r ib
VSHUFPS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8 EVEX.NDS.512.0F.W0 C6 /r ib
Category
sse1,simdfp,shunpck
Operands
Vps,Wps,Ib
Opcode
0x0FC6 /r
CPU
P3+
Tested by
t5644 
IizVSHUFPS:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD, Operand=DH
    IiEmitOpcode 0xC6
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDisp8EVEX FV32
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.0F.WIG, EVEX.NDS.128.0F.W0
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix VEX.NDS.256.0F.WIG, EVEX.NDS.256.0F.W0
    RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.0F.W0
    RET
  ENDP IizVSHUFPS::
↑ VSHUFPD
Shuffle Packed Double-FP Values
Intel reference
VSHUFPD xmm1, xmm2, xmm3/m128, imm8 VEX.NDS.128.66.0F.WIG C6 /r ib
VSHUFPD ymm1, ymm2, ymm3/m256, imm8 VEX.NDS.256.66.0F.WIG C6 /r ib
VSHUFPD xmm1{k1}{z}, xmm2, xmm3/m128/m64bcst, imm8 EVEX.NDS.128.66.0F.W1 C6 /r ib
VSHUFPD ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8 EVEX.NDS.256.66.0F.W1 C6 /r ib
VSHUFPD zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8 EVEX.NDS.512.66.0F.W1 C6 /r ib
Category
sse2,pcksclr,shunpck
Operands
Vpd,Wpd,Ib
Opcode
0x660FC6 /r
CPU
P4+
Tested by
t5644 
IizVSHUFPD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting QWORD, Operand=DH
    IiEmitOpcode 0xC6
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDisp8EVEX FV64
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    IiEmitPrefix VEX.NDS.128.66.0F.WIG, EVEX.NDS.128.66.0F.W1
    RET
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix VEX.NDS.256.66.0F.WIG, EVEX.NDS.256.66.0F.W1
    RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F.W1
    RET
  ENDP IizVSHUFPD::
↑ VSHUFF32X4
Shuffle Packed Values at 128-bit Granularity
Intel reference
VSHUFF32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8 EVEX.NDS.256.66.0F3A.W0 23 /r ib
VSHUFF32X4 zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8 EVEX.NDS.512.66.0F3A.W0 23 /r ib
Opcode
0x23
Tested by
t5646 
IizVSHUFF32X4:: PROC
    IiEmitOpcode 0x23
.op:IiAllowBroadcasting DWORD,Operand=DH
    IiDisp8EVEX FV32
    IiAllowModifier MASK
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.ymm.ymm.ymm.imm:
.ymm.ymm.mem.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W0
    RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W0
    RET
  ENDP IizVSHUFF32X4::
↑ VSHUFI32X4
Shuffle Packed Values at 128-bit Granularity
Intel reference
VSHUFI32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8 EVEX.NDS.256.66.0F3A.W0 43 /r ib
VSHUFI32X4 zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8 EVEX.NDS.512.66.0F3A.W0 43 /r ib
Opcode
0x43
Tested by
t5646 
IizVSHUFI32X4:: PROC
    IiEmitOpcode 0x43
    JMP IizVSHUFF32X4.op:
  ENDP IizVSHUFI32X4::
↑ VSHUFF64X2
Shuffle Packed Values at 128-bit Granularity
Intel reference
VSHUFF64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8 EVEX.NDS.256.66.0F3A.W1 23 /r ib
VSHUFF64X2 zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8 EVEX.NDS.512.66.0F3A.W1 23 /r ib
Opcode
0x23
Tested by
t5646 
IizVSHUFF64X2:: PROC
    IiEmitOpcode 0x23
.op:IiAllowModifier MASK
    IiAllowBroadcasting QWORD, Operand=DH
    IiDisp8EVEX FV64
    IiAllowModifier MASK
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiDispatchFormat  ymm.ymm.ymm.imm, ymm.ymm.mem.imm, zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.ymm.ymm.ymm.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W1
    RET
.ymm.ymm.mem.imm:
    IiEmitPrefix EVEX.NDS.256.66.0F3A.W1
    RET
.zmm.zmm.zmm.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W1
    RET
.zmm.zmm.mem.imm:
    IiEmitPrefix EVEX.NDS.512.66.0F3A.W1
    RET
  ENDP IizVSHUFF64X2::
↑ VSHUFI64X2
Shuffle Packed Values at 128-bit Granularity
Intel reference
VSHUFI64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8 EVEX.NDS.256.66.0F3A.W1 43 /r ib
VSHUFI64X2 zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8 EVEX.NDS.512.66.0F3A.W1 43 /r ib
Opcode
0x43
Tested by
t5646 
IizVSHUFI64X2:: PROC
    IiEmitOpcode 0x43
    JMP IizVSHUFF64X2.op:
  ENDP IizVSHUFI64X2::
↑ VPSHUFB
Packed Shuffle Bytes
Intel reference
VPSHUFB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38 00 /r
VPSHUFB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38 00 /r
VPSHUFB xmm1 {k1}{z}, xmm2, xmm3/m128 EVEX.NDS.128.66.0F38.WIG 00 /r
VPSHUFB ymm1 {k1}{z}, ymm2, ymm3/m256 EVEX.NDS.256.66.0F38.WIG 00 /r
VPSHUFB zmm1 {k1}{z}, zmm2, zmm3/m512 EVEX.NDS.512.66.0F38.WIG 00 /r
Category
ssse3,simdint
Operands
Pq,Qq | Vdq,Wdq
Opcode
0x0F3800 /r | 0x660F3800 /r
CPU
C2+
Tested by
t5648 
IizVPSHUFB:: PROC
    IiAllowModifier MASK
    IiEmitOpcode 0x00
    IiOpEn RVM
    IiModRM /r
    IiDisp8EVEX FVM
    IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
    IiEmitPrefix VEX.NDS.128.66.0F38, EVEX.NDS.128.66.0F38.WIG
    RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
    IiEmitPrefix VEX.NDS.256.66.0F38, EVEX.NDS.256.66.0F38.WIG
    RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix EVEX.NDS.512.66.0F38.WIG
    RET
  ENDP IizVPSHUFB::
↑ VPSHUFLW
Shuffle Packed Low Words
Intel reference
VPSHUFLW xmm1, xmm2/m128, imm8 VEX.128.F2.0F 70 /r ib
VPSHUFLW ymm1, ymm2/m256, imm8 VEX.256.F2.0F 70 /r ib
VPSHUFLW xmm1 {k1}{z}, xmm2/m128, imm8 EVEX.128.F2.0F.WIG 70 /r ib
VPSHUFLW ymm1 {k1}{z}, ymm2/m256, imm8 EVEX.256.F2.0F.WIG 70 /r ib
VPSHUFLW zmm1 {k1}{z}, zmm2/m512, imm8 EVEX.512.F2.0F.WIG 70 /r ib
Category
sse2,simdint,shunpck
Operands
Vdq,Wdq,Ib
Opcode
0xF20F70 /r
CPU
P4+
Tested by
t5648 
IizVPSHUFLW:: PROC
    IiAllowModifier MASK
    IiEmitOpcode 0x70
    IiOpEn RM
    IiModRM /r
    IiDisp8EVEX FVM
    IiEmitImm Operand3, BYTE
    IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
    IiEmitPrefix VEX.128.F2.0F, EVEX.128.F2.0F.WIG
    RET
.ymm.ymm.imm:
.ymm.mem.imm:
    IiEmitPrefix VEX.256.F2.0F, EVEX.256.F2.0F.WIG
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.512.F2.0F.WIG
    RET
  ENDP IizVPSHUFLW::
↑ VPSHUFHW
Shuffle Packed High Words
Intel reference
VPSHUFHW xmm1, xmm2/m128, imm8 VEX.128.F3.0F 70 /r ib
VPSHUFHW ymm1, ymm2/m256, imm8 VEX.256.F3.0F 70 /r ib
VPSHUFHW xmm1 {k1}{z}, xmm2/m128, imm8 EVEX.128.F3.0F.WIG 70 /r ib
VPSHUFHW ymm1 {k1}{z}, ymm2/m256, imm8 EVEX.256.F3.0F.WIG 70 /r ib
VPSHUFHW zmm1 {k1}{z}, zmm2/m512, imm8 EVEX.512.F3.0F.WIG 70 /r ib
Category
sse2,simdint,shunpck
Operands
Vdq,Wdq,Ib
Opcode
0xF30F70 /r
CPU
P4+
Tested by
t5648 
IizVPSHUFHW:: PROC
    IiAllowModifier MASK
    IiEmitOpcode 0x70
    IiOpEn RM
    IiModRM /r
    IiDisp8EVEX FVM
    IiEmitImm Operand3, BYTE
    IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
    IiEmitPrefix VEX.128.F3.0F, EVEX.128.F3.0F.WIG
    RET
.ymm.ymm.imm:
.ymm.mem.imm:
    IiEmitPrefix VEX.256.F3.0F, EVEX.256.F3.0F.WIG
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.512.F3.0F.WIG
    RET
  ENDP IizVPSHUFHW::
↑ VPSHUFD
Shuffle Packed Doublewords
Intel reference
VPSHUFD xmm1, xmm2/m128, imm8 VEX.128.66.0F.WIG 70 /r ib
VPSHUFD ymm1, ymm2/m256, imm8 VEX.256.66.0F.WIG 70 /r ib
VPSHUFD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8 EVEX.128.66.0F.W0 70 /r ib
VPSHUFD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8 EVEX.256.66.0F.W0 70 /r ib
VPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8 EVEX.512.66.0F.W0 70 /r ib
VPSHUFD zmm1 {k1}, zmm2/m512, imm8 MVEX.512.66.0F.W0 70 /r ib
Category
sse2,simdint,shunpck
Operands
Vdq,Wdq,Ib
Opcode
0x660F70 /r
CPU
P4+
Tested by
t5648 
IizVPSHUFD:: PROC
    IiAllowModifier MASK
    IiAllowBroadcasting DWORD, Operand=DH
    IiEmitOpcode 0x70
    IiOpEn RM
    IiModRM /r
    IiDisp8EVEX FV32
    IiDisp8MVEX Di64
    IiEmitImm Operand3, BYTE
    IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
    IiEmitPrefix VEX.128.66.0F.WIG, EVEX.128.66.0F.W0
    RET
.ymm.ymm.imm:
.ymm.mem.imm:
    IiEmitPrefix VEX.256.66.0F.WIG, EVEX.256.66.0F.W0
    RET
.zmm.zmm.imm:
.zmm.mem.imm:
    IiEmitPrefix EVEX.512.66.0F.W0, MVEX.512.66.0F.W0
    RET
  ENDP IizVPSHUFD::
↑ VFMADD233PS
Multiply First Source By Specially Swizzled Second Source and Add To Second Source Float32 Vectors
Intel reference
VFMADD233PS zmm1 {k1}, zmm2, Sf32(zmm3/mt) MVEX.NDS.512.66.0F38.W0 A4 /r
Opcode
0xA4
Tested by
t5410 
IizVFMADD233PS:: PROC
    IiAllowMaskMerging
    IiAllowRounding
    IiAllowSuppressing Swizzle=No
    IiDisp8MVEX Sf32
    IiEmitOpcode 0xA4
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  zmm.zmm.zmm, zmm.zmm.mem
.zmm.zmm.zmm:
.zmm.zmm.mem:
    IiEmitPrefix MVEX.NDS.512.66.0F38.W0
    RET
  ENDP IizVFMADD233PS::
↑ VMOVNRAPS
Store Aligned Float32 Vector With No-Read Hint
Intel reference
VMOVNRAPS mem{k1}, Df32(zmm1) MVEX.512.F2.0F.W0.EH0 29 /r
Opcode
0x29
Tested by
t5496 
IizVMOVNRAPS:: PROC
    IiEmitPrefix MVEX.512.F2.0F.W0.EH0
.d8:IiDisp8MVEX Dn32
.pf:IiAllowMaskMerging
    IiEmitOpcode 0x29
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat  mem.zmm
.mem.zmm:RET
  ENDP IizVMOVNRAPS::
↑ VMOVNRNGOAPS
Non-globally Ordered Store Aligned Float32 Vector With No-Read Hint
Intel reference
VMOVNRNGOAPS mem{k1}, Df32(zmm1) MVEX.512.F2.0F.W0.EH1 29 /r
Opcode
0x29
Tested by
t5496 
IizVMOVNRNGOAPS:: PROC
    IiEmitPrefix MVEX.512.F2.0F.W0.EH1
    JMP IizVMOVNRAPS.d8:
  ENDP IizVMOVNRNGOAPS::
↑ VMOVNRAPD
Store Aligned Float64 Vector With No-Read Hint
Intel reference
VMOVNRAPD mem{k1}, Df64(zmm1) MVEX.512.F3.0F.W1.EH0 29 /r
Opcode
0x29
Tested by
t5496 
IizVMOVNRAPD:: PROC
    IiEmitPrefix MVEX.512.F3.0F.W1.EH0
.pf:IiDisp8MVEX Di64
    JMP IizVMOVNRAPS.pf:
  ENDP IizVMOVNRAPD::
↑ VMOVNRNGOAPD
Non-globally Ordered Store Aligned Float64 Vector With No-Read Hint
Intel reference
VMOVNRNGOAPD mem{k1}, Df64(zmm1) MVEX.512.F3.0F.W1.EH1 29 /r
Opcode
0x29
Tested by
t5496 
IizVMOVNRNGOAPD:: PROC
    IiEmitPrefix MVEX.512.F3.0F.W1.EH1
    JMP IizVMOVNRAPD.pf:
  ENDP IizVMOVNRNGOAPD::

  ENDPROGRAM iiz

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